公开(公告)号：US11860811B2

公开(公告)日：2024-01-02

申请号：US17702651

申请日：2022-03-23

Applicant: Arm Limited

Inventor： Arthur Brian Laughton ,  Tessil Thomas ,  Jacob Joseph

IPC: G06F13/42 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/1668 ,  G06F13/4059 ,  G06F13/4063

Abstract: The present disclosure provides a system and methods for transferring data across an interconnect. One method includes, at a request node, receiving, from a source high speed serial controller, a write request from a source, dividing the write request into sequences of smaller write requests each having a last identifier, and sending, to a home node, the sequences of smaller write requests; and, at the home node, sending, to a destination high speed serial controller, the sequences of smaller write requests for assembly into intermediate write requests that are transmitted to a destination. Each sequence of smaller write requests is assembled into an intermediate write request based on the last identifier.

公开(公告)号：US11803506B2

公开(公告)日：2023-10-31

申请号：US17512758

申请日：2021-10-28

Applicant: Arm Limited

Inventor： Tessil Thomas ,  Anitha Kona ,  Jacob Joseph ,  Arthur Brian Laughton ,  Nandakishore Sastry

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0026

Abstract: A data processing apparatus is provided that includes communication circuitry to transmit an interconnect message to a root port using a physical address mapped to the root port. Translation circuitry encapsulates, within the interconnect message to the root port, a Peripheral Component Interconnect Express (PCIe) message to a destination, the PCIe message having routing information encoded as a PCIe bus number associated with the destination.

公开(公告)号：US10810146B2

公开(公告)日：2020-10-20

申请号：US16200205

申请日：2018-11-26

Applicant: Arm Limited

Inventor： Arthur Brian Laughton ,  Chiranjeev Acharya ,  Eduard Vardanyan

IPC: G06F13/20 ,  G06F13/40 ,  G06F13/362 ,  G06F30/30 ,  G06F111/20

Abstract: Routing circuitry 400 is provided for routing transaction requests to a selected destination node. The routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Request regulators 401, 402, 403 are provided to monitor resource usage for read, atomic and write requests, and issue circuitry 431 controls the issuing of a transaction request received from a requesting node, in dependence on resource usage monitoring performed by the request regulators. The issue circuitry controls the issuing of atomic requests in dependence on the resource usage monitored by the write request regulator and the resource usage monitored by the atomic request regulator.

公开(公告)号：US10437750B2

公开(公告)日：2019-10-08

申请号：US15850296

申请日：2017-12-21

Applicant: Arm Limited

Inventor： Arthur Brian Laughton ,  Sean James Salisbury ,  Chiranjeev Acharya ,  Eduard Vardanyan

IPC: G06F13/12 ,  G06F13/16 ,  G06F13/42

Abstract: An interconnect for providing data access between nodes of an integrated circuit, comprises a predetermined type of ingress port comprising routing circuitry responsive to a read-triggering request received from a requesting node to select from a selected egress port via which signals are to be routed to a destination node to control the destination node to return at least one read response dependent on data read from a target storage location. In response to the read-triggering request, the routing circuitry obtains a relative data width indication specifying whether read responses received at the selected egress port have a narrower data width than read responses to be provided to the requesting node by the predetermined type of ingress port, and controls allocation of resource for handling the read-triggering request or the at least one read response depending on the relative data width indication.

公开(公告)号：US20220391342A1

公开(公告)日：2022-12-08

申请号：US17336570

申请日：2021-06-02

Applicant: Arm Limited

Inventor： Arthur Brian Laughton

IPC: G06F13/40 ,  G06F16/22

Abstract: An apparatus comprises interface circuitry to receive requests and selection circuitry responsive to the interface circuitry receiving a given request to select, from a pool of items, at least one selected item to be associated with the given request. The selection circuitry comprises a plurality of nodes arranged in a tree structure, each node being configured to select m output signals from n input signals provided to that node, wherein n>m. The apparatus comprises control circuitry configured to output, in dependence on a type of the given request, a suppression signal, and the tree structure comprises a gate node configured to suppress, in response to the suppression signal having a first value, selection from input signals received from a given portion of the tree structure to prevent a subset of the pool of items from being selected for at least one type of request.

公开(公告)号：US09892072B2

公开(公告)日：2018-02-13

申请号：US14874801

申请日：2015-10-05

Applicant: ARM LIMITED

Inventor： Andrew David Tune ,  Arthur Brian Laughton ,  Daniel Adam Sara ,  Sean James Salisbury ,  Peter Andrew Riocreux

IPC: G06F13/00 ,  G06F13/364 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/4282

Abstract: Interconnect circuitry for connecting transaction masters to transaction slaves includes response modification circuitry. The response modification circuitry includes shortlist buffer circuitry storing identification for modification target transaction responses. The response modification circuitry uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master.

公开(公告)号：US20230305985A1

公开(公告)日：2023-09-28

申请号：US17702651

申请日：2022-03-23

Applicant: Arm Limited

Inventor： Arthur Brian Laughton ,  Tessil Thomas ,  Jacob Joseph

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4221 ,  G06F13/4063 ,  G06F13/4059 ,  G06F13/1668

Abstract: The present disclosure provides a system and methods for transferring data across an interconnect. One method includes, at a request node, receiving, from a source high speed serial controller, a write request from a source, dividing the write request into sequences of smaller write requests each having a last identifier, and sending, to a home node, the sequences of smaller write requests; and, at the home node, sending, to a destination high speed serial controller, the sequences of smaller write requests for assembly into intermediate write requests that are transmitted to a destination. Each sequence of smaller write requests is assembled into an intermediate write request based on the last identifier.

公开(公告)号：US10740032B2

公开(公告)日：2020-08-11

申请号：US16148295

申请日：2018-10-01

Applicant: Arm Limited

Inventor： Chiranjeev Acharya ,  Sean James Salisbury ,  Eduard Vardanyan ,  Arthur Brian Laughton

IPC: G06F3/06 ,  G06F9/52 ,  G06F30/30 ,  G06F119/18

Abstract: Data access routing circuitry 4, 6 is provided for routing data access request to a selected destination node. The data access routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Resource allocation circuitry 70, 71 is provided to control allocation of resource for handling data access requests which require a read response. The resource allocation circuitry 70, 71 reserves resource for handling the at least one type of atomic data access request and prevents use of the reserved resource 76 for handling read requests.

公开(公告)号：US10255103B2

公开(公告)日：2019-04-09

申请号：US15478443

申请日：2017-04-04

Applicant: ARM Limited

Inventor： Chiranjeev Acharya ,  Arthur Brian Laughton ,  Sean James Salisbury

IPC: G06F9/46 ,  G06F13/364 ,  G06F13/16 ,  G06F13/42 ,  G06F5/14

Abstract: Transaction handling apparatus comprises a response buffer; and tracking circuitry to store data defining each transaction issued by one or more transaction master devices and to control routing of a transaction response to a given transaction either to the response buffer or as an output to the transaction master device which issued the given transaction; the response buffer being configured to access an indicator for each buffered transaction response indicating whether a response has been output by the apparatus for a previously issued transaction, on which that buffered transaction response depends, and to output the buffered transaction response to the transaction master device which issued that transaction when the previously issued transaction has already been output by the apparatus.

公开(公告)号：US12242399B2

公开(公告)日：2025-03-04

申请号：US17678174

申请日：2022-02-23

Applicant: Arm Limited

Inventor： Jacob Joseph ,  Tessil Thomas ,  Arthur Brian Laughton ,  Anitha Kona ,  Jamshed Jalal

IPC: G06F13/00 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/1045 ,  G06F13/16

Abstract: Peripheral components, data processing systems and methods of operating such peripheral components and data processing systems are disclosed. The systems comprise an interconnect comprising a system cache, a peripheral component coupled to the interconnect, and a memory coupled to the interconnect. The peripheral component has a memory access request queue for queuing memory access requests in a receipt order. Memory access requests are issued to the interconnect in the receipt order. A memory read request is not issued to the interconnect until a completion response for all older memory write requests has been received from the interconnect. The peripheral component is responsive to receipt of a memory read request to issue a memory read prefetch request comprising a physical address to the interconnect and the interconnect is responsive to the memory read prefetch request to cause data associated with the physical address in the memory to be cached in the system cache.