公开(公告)号：US20190361486A1

公开(公告)日：2019-11-28

申请号：US15989228

申请日：2018-05-25

Applicant: Arm Limited

Inventor： Saira Samar MALIK ,  David Joseph HAWKINS ,  Andrew David TUNE ,  Guanghui GENG ,  Julian Jose Hilgemberg PONTES

IPC: G06F1/12 ,  G06F17/50

Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.

公开(公告)号：US20180225232A1

公开(公告)日：2018-08-09

申请号：US15427391

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Michael FILIPPO ,  Jamshed JALAL ,  Klas Magnus BRUCE ,  Paul Gilbert MEYER ,  David Joseph HAWKINS ,  Phanindra Kumar MANNAVA ,  Joseph Michael PUSDESRIS

IPC: G06F13/16 ,  G06F13/364 ,  G06F12/0864 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/1642 ,  G06F12/0833 ,  G06F12/0844 ,  G06F12/0864 ,  G06F13/1668 ,  G06F13/364 ,  G06F13/404 ,  G06F13/4282 ,  G06F2212/6032 ,  G06F2212/621

Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.