公开(公告)号：US20160062890A1

公开(公告)日：2016-03-03

申请号：US14640599

申请日：2015-03-06

Applicant: ARM LIMITED

Inventor： Sean James SALISBURY ,  Andrew David TUNE ,  Jamshed JALAL ,  Mark David WERKHEISER ,  Arthur LAUGHTON ,  George Robert Scott LLOYD ,  Peter Andrew RIOCREUX ,  Daniel SARA

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0815 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0673 ,  G06F2212/1021 ,  G06F2212/60

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

Abstract translation: 互连具有用于执行一致性控制操作的相关性控制电路和用于识别耦合到互连的哪些设备具有来自给定地址的缓存数据的窥探过滤器。 当在窥探过滤器中查找地址并丢失时，并且没有可用的备用侦听筛选器条目，则侦听筛选器将选择与受害者地址相对应的受害者条目，并发出无效的事务以使本地缓存的数据副本无效 由受害者确定。 用于执行数据访问事务的一致性检查操作的一致性控制电路被重新用于执行由窥探过滤器发出的无效事务的一致性控制操作。 这大大降低了窥探滤波器的电路复杂度。

公开(公告)号：US20160203093A1

公开(公告)日：2016-07-14

申请号：US14959170

申请日：2015-12-04

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Peter Andrew RIOCREUX ,  Sean James SALISBURY ,  Daniel Adam SARA ,  George Robert Scott LLOYD

IPC: G06F13/364 ,  G06F13/42 ,  G06F13/40 ,  G06F12/08

CPC classification number: G06F13/364 ,  G06F12/0815 ,  G06F13/404 ,  G06F13/4282 ,  G06F2212/621

Abstract: An interconnect, and method of operation of an interconnect, are provided for connecting a plurality of master devices and a plurality of slave devices. Hazard management circuitry is used to serialise transactions to overlapping addresses. In addition, gating circuitry ensures ordered write observation (OWO) behaviour at an interface to one or more of the master devices, the gating circuitry receiving write address transfers of write transactions and performing a gating operation to gate onward propagation of the write address transfers to the slave devices in order to ensure the OWO behaviour. The gating circuitry performs the gating operation under control of the hazard management circuitry. Hence, for write transactions that are subjected to hazard checking by the hazard management circuitry, this removes the need to implement any other processes to specifically manage OWO behaviour for those write transactions.

Abstract translation: 提供了用于连接多个主设备和多个从设备的互连的互连和操作方法。 危险管理电路用于将交易序列化到重叠地址。 另外，门控电路确保在与一个或多个主设备的接口上的有序写入观察（OWO）行为，门控电路接收写入事务的写入地址传输，并且执行门控操作以将写入地址传输的门向前传播到 从设备为了确保OWO的行为。 门控电路在危害管理电路的控制下执行门控操作。 因此，对于由危险管理电路进行危险检查的写入事务，这样就不需要实施任何其他进程来专门管理这些写入事务的OWO行为。

公开(公告)号：US20170315947A1

公开(公告)日：2017-11-02

申请号：US15139559

申请日：2016-04-27

Applicant: ARM Limited

Inventor： Ian David ANDREWS ,  Andrew David TUNE ,  Daniel Adam SARA ,  George Robert Scott LLOYD

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

Abstract: A crossbar switch comprises two or more data inputs 10, two or more data outputs 100, a buffer 30 between the inputs and the outputs, an arbiter 52 associated with each output and configured to select data from one of the inputs when there is contention at the output, a bypass 32 associated with the buffer so that the buffer can be enabled or disabled, and a buffer controller 60 configured to enable or disable the buffer. The buffer controller further includes an accumulator 70 configured to assess whether a time-based average of the contention rate, or an average injection rate, at the output associated with the buffer, has reached a predetermined threshold. This prevents the buffer being enabled when the contention is only intermittent, which reduces power consumption without significant loss of performance.