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    METHOD AND APPARATUS FOR DATA PROCESSING OPERATION
    2.
    发明申请
    METHOD AND APPARATUS FOR DATA PROCESSING OPERATION 有权

    公开(公告)号：US20220066739A1

    公开(公告)日：2022-03-03

    申请号：US17005046

    申请日：2020-08-27

    Applicant: Arm Limited

    Inventor： Daren CROXFORD ,  Guy LARRI

    IPC: G06F7/544 ,  G06F16/25 ,  G06N3/04 ,  H03M7/24 ,  G06K9/62

    Abstract: A system includes a fixed-point accumulator for storing numbers in an anchored fixed-point number format, a data interface arranged to receive a plurality of weight values and a plurality of data values represented in a floating-point number format, and logic circuitry. The logic circuitry is configured to: determine an anchor value indicative of a value of a lowest significant bit of the anchored fixed-point number format; convert at least a portion of the plurality of data values to the anchored fixed-point number format; perform MAC operations between the converted at least portion and respective weight values, using fixed-point arithmetic, to generate an accumulation value in the anchored fixed-point number format; and determine an output element of a later of a neural network in dependence on the accumulation value.

    TRACKING THE CONTENT OF A CACHE
    3.
    发明申请
    TRACKING THE CONTENT OF A CACHE 有权
    跟踪缓存的内容

    公开(公告)号：US20160328320A1

    公开(公告)日：2016-11-10

    申请号：US14702972

    申请日：2015-05-04

    Applicant: ARM LIMITED

    Inventor： Miles Robert DOOLEY ,  Todd RAFACZ ,  Guy LARRI

    IPC: G06F12/08

    CPC classification number: G06F12/0895 ,  G06F12/0864 ,  G06F12/1027 ,  Y02B70/30 ,  Y02D10/13

    Abstract: A cache is provided comprising a plurality of ways, each way of the plurality of ways comprising a data array, wherein a data item stored by the cache is stored in the data array of one of the plurality of ways. A way tracker of the cache has a plurality of entries, each entry of the plurality of entries for storing a data item identifier and for storing, in association with the data item identifier, an indication of a selected way of the plurality of ways to indicate that a data item identified by the data item identifier is stored in the selected way. Each entry of the way tracker is further for storing a miss indicator in association with the data item identifier, wherein the miss indicator is set by the cache when a lookup for a data item identified by that data item identifier has resulted in a cache miss. A corresponding method of caching data is also provided.

    Abstract translation: 提供包括多个方式的高速缓存，多个方式的每一路包括数据阵列，其中高速缓存存储的数据项被存储在多个方式之一的数据阵列中。 高速缓存的方式跟踪器具有多个条目，多个条目的每个条目用于存储数据项标识符，并且用于与数据项标识符相关联地存储指示多个方式的所选方式的指示 以所选择的方式存储由数据项标识符标识的数据项。 方式跟踪器的每个条目还用于存储与数据项标识符相关联的未命中指示符，其中当由该数据项标识符标识的数据项的查找导致高速缓存未命中时，该高速缓存设置该未命中指示符。 还提供了缓存数据的相应方法。

    AUTHENTICATION CODE GENERATION/CHECKING INSTRUCTIONS
    4.
    发明公开
    AUTHENTICATION CODE GENERATION/CHECKING INSTRUCTIONS 审中-公开

    公开(公告)号：US20230259605A1

    公开(公告)日：2023-08-17

    申请号：US18005150

    申请日：2021-06-23

    Applicant: Arm Limited

    Inventor： Guy LARRI

    IPC: G06F21/44 ,  G06F21/52 ,  G06F21/71 ,  G06F21/55 ,  G06F9/30

    CPC classification number: G06F21/44 ,  G06F21/52 ,  G06F21/71 ,  G06F21/554 ,  G06F9/3016 ,  G06F2221/034

    Abstract: An apparatus comprises processing circuitry to execute instructions, and decode circuitry to decode the instructions for execution by the processing circuitry. The decode circuitry is responsive to an authentication code generation instruction specifying a first source value to control the processing circuitry to generate an authentication code dependent on the first source value, and store the authentication code to a memory location associated with a store address formed using a value obtained from a register. By providing a single instruction, this reduces register pressure enabling improved performance by avoiding unnecessary load/store operations, and makes compilation of code using the authentication code generation instruction simpler. Because it does not store the result of the cryptographic function in the register bank, it also enables simple in-order CPU designs to hide the latency of slow cryptographic computations by allowing subsequent instructions to start executing before the cryptographic computation has completed.

    A TECHNIQUE FOR HANDLING TRANSACTIONS IN A SYSTEM EMPLOYING TRANSACTIONAL MEMORY
    6.
    发明公开
    A TECHNIQUE FOR HANDLING TRANSACTIONS IN A SYSTEM EMPLOYING TRANSACTIONAL MEMORY 审中-公开

    公开(公告)号：US20230315510A1

    公开(公告)日：2023-10-05

    申请号：US18245659

    申请日：2021-08-02

    Applicant: ARM LIMITED

    Inventor： Timothy HAYES ,  David Hennah MANSELL ,  Alasdair GRANT ,  Guy LARRI

    IPC: G06F9/46 ,  G06F9/30

    CPC classification number: G06F9/467 ,  G06F9/30098

    Abstract: An apparatus and method are provided for handling transactions in a system employing transactional memory. The apparatus has processing circuitry for performing data processing in response to instructions, and transactional memory support circuitry for supporting execution of a transaction within a thread of data processing by the processing circuitry. The transaction comprises a sequence of instructions executed speculatively and for which the processing circuitry prevents commitment of results of those instructions until the transaction has reached a transaction end point. The transactional memory support circuitry comprises abort event detection circuitry that causes execution of the transaction to be aborted when an abort event is detected before the transaction has reached the transaction end point, and which causes abort status information to be stored for later reference when determining whether to retry execution of the transaction.

    HUMAN-MACHINE INTERFACE SYSTEM
    7.
    发明申请
    HUMAN-MACHINE INTERFACE SYSTEM 有权

    公开(公告)号：US20220308667A1

    公开(公告)日：2022-09-29

    申请号：US17211107

    申请日：2021-03-24

    Applicant: Arm Limited

    Inventor： Daren CROXFORD ,  Guy LARRI

    IPC: G06F3/01 ,  G06F3/033 ,  G06N3/08 ,  G06N3/04 ,  G05B13/02 ,  A63F13/212

    Abstract: A human-machine interface system comprises a sensor configured to generate data associated with a human movement, such as measured electrical signals or data from an accelerometer. A measurement unit of the human-machine interface measures user movement over time to generate a sequence of measured user movement data. A processor processes the data associated with a human movement from the sensor using a trained neural network to determine one or more predicted user actions. A comparison unit compares the one or more predicted user actions with one or more user actions obtained from the sequence of measured user movement data. A control unit uses the predicted user actions to control a process in an information processing apparatus in dependence upon the comparison performed by the comparison unit.

    APPARATUS WITH AT LEAST ONE RESOURCE HAVING THREAD MODE AND TRANSACTION MODE, AND METHOD
    8.
    发明申请
    APPARATUS WITH AT LEAST ONE RESOURCE HAVING THREAD MODE AND TRANSACTION MODE, AND METHOD 审中-公开

    公开(公告)号：US20170329626A1

    公开(公告)日：2017-11-16

    申请号：US15531836

    申请日：2015-11-24

    Applicant: ARM LIMITED

    Inventor： Stephan DIESTELHORST ,  Matthew James HORSNELL ,  Guy LARRI

    IPC: G06F9/46 ,  G06F9/52 ,  G06F9/50

    Abstract: An apparatus (2) has processing circuitry (6) having access to a first processing resource (20-0) and a second processing resource (20-3). A first thread can be processed using the first processing resource. In a thread mode the second processing resource (20-3) can be used to process a second thread while in a transaction mode the second processing resource (20-3) can be used to process a transaction of the first thread comprising a number of speculatively performed operations for which results are committed at the end of the transaction. By sharing resources for supporting additional threads and supporting transactions, circuit area and power consumption can be reduced.

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