公开(公告)号：US09892072B2

公开(公告)日：2018-02-13

申请号：US14874801

申请日：2015-10-05

Applicant: ARM LIMITED

Inventor： Andrew David Tune ,  Arthur Brian Laughton ,  Daniel Adam Sara ,  Sean James Salisbury ,  Peter Andrew Riocreux

IPC: G06F13/00 ,  G06F13/364 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/4282

Abstract: Interconnect circuitry for connecting transaction masters to transaction slaves includes response modification circuitry. The response modification circuitry includes shortlist buffer circuitry storing identification for modification target transaction responses. The response modification circuitry uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master.

公开(公告)号：US10303624B2

公开(公告)日：2019-05-28

申请号：US15273932

申请日：2016-09-23

Applicant: ARM LIMITED

Inventor： Andrew David Tune ,  Peter Andrew Riocreux ,  Alessandro Grande

IPC: H04L12/937 ,  G06F13/14

Abstract: Arbitrating and multiplexing circuitry for performing an arbitration between a plurality of inputs and a selection of at least one of said plurality of inputs to provide an output comprises arbitrating tree circuitry having X arbitrating levels, where X is an integer greater than one; and multiplexing tree circuitry having Y multiplexing levels, where Y is an integer greater than one; wherein (i) said Y multiplexing levels comprise a first set of said multiplexing levels upstream of a second set of said multiplexing levels; (ii) said first set of said multiplexing levels is configured to operate in parallel with at least some of said X arbitrating levels, whereby said first set of multiplexing levels is configured to perform a partial selection in parallel with said arbitration performed by said X arbitrating levels; and (iii) said second set of said multiplexing levels is configured to operate in series with said X arbitrating levels, whereby said second set of multiplexing levels completes said selection to provide said output following completion of and in dependence upon said arbitration.

公开(公告)号：US09852088B2

公开(公告)日：2017-12-26

申请号：US14628331

申请日：2015-02-23

Applicant: ARM LIMITED

Inventor： Andrew David Tune ,  Daniel Sara ,  Sean James Salisbury ,  Arthur Laughton ,  Peter Andrew Riocreux

IPC: G06F13/16 ,  G06F13/00

CPC classification number: G06F13/1626 ,  G06F13/1673

Abstract: A system-on-check integrated circuit 2 includes interconnect circuitry 4 connecting a plurality of transaction sources to a plurality of transaction destinations. The interconnect circuitry 4 includes a reorder buffer for buffering access transactions and hazard checking circuitry 46, 48, 50, 52 for performing hazard checks, such as point-of-serialization checks and identifier reuse checks. Check suppression circuitry 62, 64, 66, 68 serves to suppress one or more hazard checks depending upon one or more state variables that themselves depend upon access transactions other than the access transaction for which the hazard checking is or is not to be suppressed. As an example, hazard checking may be suppressed if it is known that there are no other access transactions currently buffered within the reorder buffer 26 or alternatively no other access transactions from the same transaction source buffered within the reorder buffer 26.

公开(公告)号：US09477623B2

公开(公告)日：2016-10-25

申请号：US13960128

申请日：2013-08-06

Applicant: ARM LIMITED

Inventor： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

IPC: G06F13/16 ,  G06F13/362 ,  G06F13/364

CPC classification number: G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

Abstract: Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.

公开(公告)号：US11379152B2

公开(公告)日：2022-07-05

申请号：US16898781

申请日：2020-06-11

Applicant: Arm Limited

Inventor： Andrew Brookfield Swaine ,  Peter Andrew Riocreux

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/1027

Abstract: An apparatus comprises transaction handling circuitry to issue memory access transactions, each memory access transaction specifying an epoch identifier indicative of a current epoch in which the memory access transaction is issued; transaction tracking circuitry to track, for each of at least two epochs, a number of outstanding memory access transactions issued in that epoch; barrier termination circuitry to signal completion of a barrier termination command when the transaction tracking circuitry indicates that there are no outstanding memory access transactions remaining which were issued in one or more epochs preceding a barrier point; and epoch changing circuitry to change the current epoch to a next epoch, in response to a barrier point signal representing said barrier point. This helps to reduce the circuit area overhead for tracking completion of memory access transactions preceding a barrier point.

公开(公告)号：US11288207B2

公开(公告)日：2022-03-29

申请号：US16834171

申请日：2020-03-30

Applicant: Arm Limited

Inventor： Peter Andrew Riocreux

IPC: G06F12/1045 ,  G06F9/46 ,  G06F12/084 ,  G06F12/0831

Abstract: Apparatus comprises address translation circuitry configured to access translation data defining a set of memory address translations; transaction handling circuitry to receive translation transactions and to receive invalidation transactions, each translation transaction defining one or more input memory addresses in an input memory address space to be translated to respective output memory addresses in an output memory address space, in which the transaction handling circuitry is configured to control the address translation circuitry to provide the output memory address as a translation response; in which each invalidation transaction defines at least a partial invalidation of the translation data; transaction tracking circuitry to associate an invalidation epoch, of a set of at least two invalidation epochs, with each translation transaction and with each invalidation transaction; and invalidation circuitry to store data defining a given invalidation transaction and, for translation transactions having the same invalidation epoch as the given invalidation transaction and handled by the address translation circuitry subsequent to the invalidation circuitry storing the data defining the given invalidation transaction, to process those translation transactions to indicate that a translation transaction is invalidated when the invalidation defined by the given invalidation transaction applies to that translation transaction; the invalidation circuitry being configured to forward at least an acknowledgement of the invalidation transaction for further processing by other apparatus in response to storage of the data by the invalidation circuitry.

公开(公告)号：US10592439B2

公开(公告)日：2020-03-17

申请号：US16386321

申请日：2019-04-17

Applicant: ARM Limited

Inventor： Andrew David Tune ,  Peter Andrew Riocreux ,  Alessandro Grande

IPC: G06F13/14

Abstract: Arbitrating circuitry arbitrates between a plurality of inputs and a selection of at least one of said plurality of inputs. The arbitrating circuitry includes an array of interconnected arbiter devices operating with respect to a set of Q inputs. The array comprises M sub-levels with at least a first sub-level having T arbiter devices each operating with respect to U inputs, where Q=UM and Q=TU. For each sub-level other than a first sub-level, each arbiter device in a sub-level receives as input requests signals indicating an arbitration outcome for two or more arbiter devices in a preceding sub-level and arbitrates between those input requests.

公开(公告)号：US09928195B2

公开(公告)日：2018-03-27

申请号：US14959170

申请日：2015-12-04

Applicant: ARM LIMITED

Inventor： Andrew David Tune ,  Peter Andrew Riocreux ,  Sean James Salisbury ,  Daniel Adam Sara ,  George Robert Scott Lloyd

IPC: G06F13/00 ,  G06F13/36 ,  G06F13/38 ,  G06F13/42 ,  G06F13/364 ,  G06F12/0815 ,  G06F13/40

CPC classification number: G06F13/364 ,  G06F12/0815 ,  G06F13/404 ,  G06F13/4282 ,  G06F2212/621

Abstract: An interconnect, and method of operation of an interconnect, are provided for connecting a plurality of master devices and a plurality of slave devices. Hazard management circuitry is used to serialize transactions to overlapping addresses. In addition, gating circuitry ensures ordered write observation (OWO) behavior at an interface to one or more of the master devices, the gating circuitry receiving write address transfers of write transactions and performing a gating operation to gate onward propagation of the write address transfers to the slave devices in order to ensure the OWO behavior. The gating circuitry performs the gating operation under control of the hazard management circuitry. Hence, for write transactions that are subjected to hazard checking by the hazard management circuitry, this removes the need to implement any other processes to specifically manage OWO behavior for those write transactions.

公开(公告)号：US09507716B2

公开(公告)日：2016-11-29

申请号：US14640599

申请日：2015-03-06

Applicant: ARM LIMITED

Inventor： Sean James Salisbury ,  Andrew David Tune ,  Jamshed Jalal ,  Mark David Werkheiser ,  Arthur Laughton ,  George Robert Scott Lloyd ,  Peter Andrew Riocreux ,  Daniel Sara

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F12/0815 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0673 ,  G06F2212/1021 ,  G06F2212/60

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

Abstract translation: 互连具有用于执行一致性控制操作的相关性控制电路和用于识别耦合到互连的哪些设备具有来自给定地址的缓存数据的窥探过滤器。 当在窥探过滤器中查找地址并丢失时，并且没有可用的备用侦听筛选器条目，则侦听筛选器将选择与受害者地址相对应的受害者条目，并发出无效的事务以使本地缓存的数据副本无效 由受害者确定。 用于执行数据访问事务的一致性检查操作的一致性控制电路被重新用于执行由窥探过滤器发出的无效事务的一致性控制操作。 这大大降低了窥探滤波器的电路复杂度。