公开(公告)号：US20040136141A1

公开(公告)日：2004-07-15

申请号：US10733848

申请日：2003-12-11

申请人： AVX CORPORATION

发明人： George Korony ,  Andrew P. Ritter

IPC分类号： H01G004/228

CPC分类号： H01G4/38 ,  H01G4/232 ,  H01G4/30

摘要： A transmission line capacitor includes at least two side-by-side capacitor portions spaced apart between a separating portion all contained in a single monolithic body. Such transmission line capacitors provide specific capacitor functionality for parallel transmission lines in a printed circuit board environment, while also maintaining a desired impedance value between the transmission paths. The transmission line capacitors offer both biasing functionality for blocking undesired DC voltages as well as AC coupling functionality for passing AC voltage signals with preserved data integrity. A first embodiment may be formed with a dielectric material having a relatively low dielectric constant, allowing high capacitor nullheightnull with fixed spacing between distinct capacitive structures. Another embodiment may be formed with a relative high K dielectric and then slotted with an air gap between capacitive structures. Yet another embodiment may be formed with a relatively high K dielectric material, and with a relatively low K material provided in between capacitive structures. A still further embodiment concerns a transmission line capacitor design formed with high K and low K dielectric materials punched into a monolithic thin-film device.

摘要翻译： 传输线电容器包括至少两个并排电容器部分，其间分离在全部包含在单个整体中的分离部分。 这样的传输线电容器为印刷电路板环境中的并行传输线提供特定的电容器功能，同时还在传输路径之间保持期望的阻抗值。 传输线电容器提供用于阻止不期望的直流电压的偏置功能以及用于传递具有保持的数据完整性的交流电压信号的交流耦合功能。 第一实施例可以由具有相对低的介电常数的电介质材料形成，允许在不同的电容结构之间具有固定间隔的高电容器“高度”。 另一个实施例可以用相对高的K电介质形成，然后与电容结构之间的气隙开槽。 另一个实施例可以用相对高的K电介质材料形成，并且具有设置在电容结构之间的相对低的K材料。 又一实施例涉及用高K和低K电介质材料冲压成单片薄膜器件形成的传输线电容器设计。

公开(公告)号：US20040257748A1

公开(公告)日：2004-12-23

申请号：US10818951

申请日：2004-04-06

申请人： AVX Corporation

发明人： Andrew P. Ritter ,  Robert Heistand II ,  John L. Galvagni ,  Sriram Dattaguru ,  Jeffrey A. Horn ,  Richard A. Ladew

IPC分类号： H01G004/228

CPC分类号： H01G4/012 ,  H01G4/232 ,  H01G4/30 ,  H01L2924/01029 ,  Y10T29/42 ,  Y10T29/43 ,  Y10T29/435

摘要： A multilayer electronic component includes a plurality of dielectric layers interleaved with a plurality of internal electrode elements and a plurality of internal anchor tabs. Portions of the internal electrode elements and anchor tabs are exposed along the periphery of the electronic component in one or more aligned columns. Each exposed portion is within a predetermined distance from other exposed portions in a given column such that bridged terminations may be formed by depositing one or more plated termination materials over selected of the respectively aligned columns. Internal anchor tabs may be provided and exposed in prearranged relationships with other exposed conductive portions to help nucleate metallized plating material along the periphery of a device. External anchor tabs or lands may be provided to form terminations that extend to top and/or bottom surfaces of the device. Selected of the conductive elements may be formed by a finite volume percentage of ceramic material for enhanced durability, and external lands may be thicker than internal conductive elements and/or may also be embedded in top and/or bottom component surfaces. A variety of potential internal electrode configurations are possible including ones configured for orientation-insensitive component mounting and for high density peripheral termination interdigitated capacitors.

摘要翻译： 多层电子部件包括与多个内部电极元件和多个内部固定突片交错的多个电介质层。 内部电极元件和锚定片的部分沿着电子元件的外围在一个或多个对齐的列中露出。 每个暴露部分在与给定列中的其它暴露部分预定距离内，使得桥接端接可以通过在选定的分别对准的柱上沉积一个或多个电镀终止材料而形成。 可以提供内部锚定突片并以与其它暴露的导电部分的预定关系暴露，以帮助沿着装置的周边使金属化电镀材料成核。 可以提供外部锚定片或平台以形成延伸到装置的顶部和/或底部表面的终端。 选择的导电元件可以由有限体积百分比的陶瓷材料形成，以增强耐久性，并且外部焊盘可以比内部导电元件厚，和/或也可以嵌入在顶部和/或底部部件表面中。 各种潜在的内部电极配置是可能的，包括被配置用于定向不敏感元件安装和用于高密度外围端接叉指电容器的构造。

公开(公告)号：US20040174656A1

公开(公告)日：2004-09-09

申请号：US10674906

申请日：2003-09-30

申请人： AVX Corporation

发明人： Jason MacNeal ,  John L. Galvagni ,  Andrew P. Ritter

IPC分类号： H01G004/228

CPC分类号： H01G4/232 ,  H01G4/30

摘要： A window via capacitor comprises a stacked multilayer configuration of at least one bottom layer, a plurality of first and second layers, a transition layer and a cover layer. Each first and second layer is preferably characterized by a sheet of dielectric material with a respective first or second electrode plate provided thereon. Adjacent first and second electrode plates form opposing active capacitor plates in the multilayer configuration. Portions of each first and second electrode plate extend to and are exposed on selected periphery side portions. Electrode portions of each transition layer are aligned in respective similar locations to the first and second electrode plates such that peripheral terminations can connect selected electrode portions of a first polarity together and selected portions of the opposing polarity together. Solder balls may also be applied to window vias to yield a capacitor compatible with BGA mounting technology.

摘要翻译： 窗口通孔电容器包括至少一个底层，多个第一和第二层，过渡层和覆盖层的堆叠多层结构。 每个第一层和第二层的特征在于一层电介质材料，其上设有相应的第一或第二电极板。 相邻的第一和第二电极板在多层结构中形成相对的有源电容器板。 每个第一和第二电极板的部分延伸到并且在选定的外围侧部分上露出。 每个过渡层的电极部分在与第一和第二电极板的各自相似的位置中对准，使得外围终端可以将选定的第一极性的电极部分连接在一起并将相对极性的选定部分连接在一起。 焊球也可以应用于窗口通孔，以产生与BGA安装技术兼容的电容器。

公开(公告)号：US20040042155A1

公开(公告)日：2004-03-04

申请号：US10446464

申请日：2003-05-28

申请人： AVX CORPORATION

发明人： Andrew P. Ritter ,  John L. Galvagni

IPC分类号： H01G004/228

CPC分类号： H01G4/30 ,  H01G4/2325

摘要： A multilayer ceramic capacitor assembly capable of exhibiting low high-frequency inductance and a controlled equivalent series resistance (ESR) while maintaining a useful capacitance value includes respective pluralities of first and second electrode elements interleaved to form a stack. Controlled ESR is achieved either through inclusion of specific types of materials or through alteration of the shape of various component parts. A resistive material may be used in typical end terminations, via terminations, electrode elements or connective tab structures. Additionally, the dielectric may be made lossy so as to enhance resistivity without overly affecting device capacitance. Still further, an additional layer of resistive material may be added to an outer device surface to connect filled-via terminations to end terminations or radial resistive prints may be used to only partially fill the vias. Finally, various electrode element configurations, such as flat plate, serpentine, mesh, L-, O- or U-shaped patterns, may be employed.

摘要翻译： 能够表现出低的高频电感和受控的等效串联电阻（ESR）同时保持有用的电容值的多层陶瓷电容器组件包括相互交织以形成叠层的多个第一和第二电极元件。 通过包含特定类型的材料或通过改变各种组分部件的形状来实现受控ESR。 电阻材料可用于典型的端接端子，通过端子，电极元件或连接片结构。 此外，电介质可以是有损的，以便增强电阻率而不会过度影响器件电容。 此外，可以将附加的电阻材料层添加到外部器件表面以将填充通孔端子连接到端部端子，或者径向电阻印刷可用于仅部分填充通孔。 最后，可以采用诸如平板，蛇形，网状，L-，O-或U形图案的各种电极元件结构。

公开(公告)号：US20040090732A1

公开(公告)日：2004-05-13

申请号：US10632514

申请日：2003-08-01

申请人： AVX Corporation

发明人： Andrew P. Ritter ,  Robert Heistand II ,  John L. Galvagni ,  Sriram Dattaguru

IPC分类号： H01G004/228

CPC分类号： H01C1/14 ,  C23C18/1605 ,  C23C18/1639 ,  C23C18/1886 ,  H01C7/008 ,  H01C7/10 ,  H01G4/005 ,  H01G4/232 ,  H01G4/30 ,  H05K1/181 ,  Y02P70/611 ,  Y10T29/43 ,  Y10T29/435

摘要： Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on one or both of top and bottom surfaces of a monolithic structure can facilitate the formation of selective wrap-around plated terminations. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.

公开(公告)号：US20030231457A1

公开(公告)日：2003-12-18

申请号：US10409023

申请日：2003-04-08

申请人： AVX Corporation

发明人： Andrew P. Ritter ,  Robert Heistand II ,  John L. Galvagni ,  Sriram Dattaguru

IPC分类号： H01G004/228

CPC分类号： H01G4/30 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/32 ,  C23C18/38 ,  C23C18/48 ,  C23C28/021 ,  C23C28/023 ,  C25D3/56 ,  C25D5/02 ,  C25D5/34 ,  C25D7/00 ,  H01C1/14 ,  H01C7/008 ,  H01C7/10 ,  H01C17/28 ,  H01F41/04 ,  H01G4/005 ,  H01G4/008 ,  H01G4/012 ,  H01G4/06 ,  H01G4/12 ,  H01G4/228 ,  H01G4/232 ,  H05K3/02 ,  H05K3/403 ,  H05K2201/09709 ,  Y10T29/417 ,  Y10T29/42 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49099 ,  Y10T29/49101

摘要： Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.

摘要翻译： 公开了改进的多层电子部件的端接特征。 单片组件设置有电镀端接，从而消除或大大简化了对典型厚膜端接条的需要。 这种终端技术消除了许多典型的终端问题，并且能够以更细的间距实现更高数量的终端，这对于较小的电子部件可能是特别有益的。 受电镀的端子通过暴露的内部电极接线片和附加的锚固片部分被引导和锚固，该锚固片部分可任选地延伸到多层部件的覆盖层。 这种锚定片可以相对于芯片结构位于内部或外部，以使附加的金属化电镀材料成核。 位于整体式结构的顶部和底部的外部锚固片可有助于形成环绕电镀终端。 所公开的技术可以与多个单片多层组件一起使用，包括交错电容器，多层电容器阵列和集成无源组件。 可以采用各种不同的电镀技术和终止材料来形成受试者自确定的电镀终端。