公开(公告)号：US20070033485A1

公开(公告)日：2007-02-08

申请号：US11487063

申请日：2006-07-13

申请人： Aaron Cohen ,  Keshab Parhi

发明人： Aaron Cohen ,  Keshab Parhi

IPC分类号： H03M13/00

CPC分类号： H03M13/1182 ,  H03M13/6561

摘要： Encoders and methods for designing encoders for Low Density Parity Check (LDPC) and other block codes are presented. An efficient and systematic method for designing partially parallel encoders is presented. A parallelism factor is selected such that the end result for the encoder is similar to the partially parallel G matrix multiplication method. In addition to the method an initial circuit is given for the G matrix multiplication encoder and the RU encoder. A circuit for the hybrid encoder is presented which achieves less power consumption and smaller area than an equivalent encoder based on the G matrix multiplication with a smaller critical path than previous encoders.

摘要翻译： 提出了用于设计低密度奇偶校验（LDPC）编码器的编码器和方法以及其他块代码。 提出了一种设计部分并行编码器的高效，系统的方法。 选择并行因子使得编码器的最终结果类似于部分并行的G矩阵乘法方法。 除了该方法之外，还给出了G矩阵乘法编码器和RU编码器的初始电路。 提出了一种用于混合编码器的电路，其基于与先前编码器相比较小的关键路径的G矩阵乘法，比等效编码器实现更少的功率消耗和更小的面积。

公开(公告)号：US20080109709A1

公开(公告)日：2008-05-08

申请号：US11951822

申请日：2007-12-06

申请人： Chao Cheng ,  Keshab Parhi

发明人： Chao Cheng ,  Keshab Parhi

IPC分类号： H03M13/27 ,  G06F11/10

CPC分类号： H03M13/4107 ,  H03M13/395 ,  H03M13/3961

摘要： A low-latency, high-throughput rate Viterbi decoder implemented in a K1-nested layered look-ahead (LLA) manner, combines K1-trellis steps, with look-ahead step M, where K

摘要翻译： 以K1嵌套分层预先（LLA）方式实现的低等待时间，高吞吐率维特比解码器将K1-网格步骤与先行步骤M组合，其中K

公开(公告)号：US20070033484A1

公开(公告)日：2007-02-08

申请号：US11487042

申请日：2006-07-13

申请人： Sang-Min Kim ,  Keshab Parhi ,  Renfei Liu

发明人： Sang-Min Kim ,  Keshab Parhi ,  Renfei Liu

IPC分类号： H03M13/00

CPC分类号： H03M13/1151 ,  H03M13/1111 ,  H03M13/1137

摘要： A memory address generation method and circuit architecture for time-multiplexed RS-based LDPC code decoder is presented. The method is developed for non quasi-cyclic RS-based LDPC code decoder implementation. A circuit for the memory address generation method achieves low area. High throughput time-multiplexed RS-based LDPC code decoder design models and circuit architectures are presented. The decoder models are specifically developed for 10BASE-T (10-Gigabit Ethernet Transceiver Over Copper) system. These time-multiplexed architectures enable higher throughput with lower area.

摘要翻译： 提出了一种用于时间复用的基于RS的LDPC码解码器的存储器地址生成方法和电路架构。 该方法被开发用于非准循环的基于RS的LDPC码解码器实现。 用于存储器地址生成方法的电路实现了低的面积。 提出了高吞吐量时间复用的基于RS的LDPC码解码器设计模型和电路架构。 解码器型号专为10BASE-T（万兆以太网收发器铜缆）系统而开发。 这些时分复用架构能够实现更低的面积的更高的吞吐量。

公开(公告)号：US20060056521A1

公开(公告)日：2006-03-16

申请号：US11225383

申请日：2005-09-13

申请人： Keshab Parhi ,  Yongru Gu

发明人： Keshab Parhi ,  Yongru Gu

IPC分类号： H04B14/04 ,  H04L27/04

CPC分类号： H04L25/03343 ,  H04L25/497

摘要： The invention relates to techniques for implementing high-speed precoders, such as Tomlinson-Harashima (TH) precoders. In one aspect of the invention, look-ahead techniques are utilized to pipeline a TH precoder, resulting in a high-speed TH precoder. These techniques may be applied to pipeline various types of TH precoders, such as Finite Impulse Response (FIR) precoders and Infinite Impulse Response (IIR) precoders. In another aspect of the invention, parallel processing multiple non-pipelined TH precoders results in a high-speed parallel TH precoder design. Utilization of high-speed TH precoders may enable network providers to for example, operate 10 Gigabit Ethernet with copper cable rather than fiber optic cable.

摘要翻译： 本发明涉及用于实现诸如Tomlinson-Harashima（TH）预编码器的高速预编码器的技术。 在本发明的一个方面，利用先行技术来管理TH预编码器，导致高速TH预编码器。 这些技术可以应用于管道各种类型的TH预编码器，例如有限脉冲响应（FIR）预编码器和无限脉冲响应（IIR）预编码器。 在本发明的另一方面，并​​行处理多个非流水线TH预编码器导致高速并行TH预编码器设计。 使用高速TH预编码器可以使网络供应商能够使用铜缆而不是光纤电缆来操作万兆以太网。

公开(公告)号：US20070014378A1

公开(公告)日：2007-01-18

申请号：US11487067

申请日：2006-07-13

申请人： Keshab Parhi ,  Yongru Gu

发明人： Keshab Parhi ,  Yongru Gu

IPC分类号： H04B7/02 ,  H04B7/10

CPC分类号： H04B3/32

摘要： A method to efficiently deal with FEXT crosstalk in wireline communication system via MIMO equalization is presented. A MIMO-DFE based receiver architecture is developed to demonstrate the advantage over the traditional receiver design. A MIMO structure for systems with TH precoding is also developed for 10GBASE-T application. The proposed architecture overcomes the limitation of the traditional schemes and achieves a better SNR performance and lower receiver complexity. The proposed method relies on the fact that FEXT inherently contains information about the symbols transmitted from the three far end transmitters and it can be viewed as a signal rather than noise. Therefore, MIMO techniques are applied to turn FEXT into a benefit for the receiver design.

摘要翻译： 提出了一种通过MIMO均衡有效处理有线通信系统中FEXT串扰的方法。 开发了基于MIMO-DFE的接收机架构，以证明与传统接收机设计相比的优势。 还针对10GBASE-T应用开发了具有TH预编码的系统的MIMO结构。 所提出的架构克服了传统方案的局限性，实现了更好的SNR性能和更低的接收机复杂度。 所提出的方法依赖于FEXT固有地包含关于从三个远端发射机发射的符号的信息的事实，并且它可以被视为信号而不是噪声。 因此，应用MIMO技术将FEXT转化为接收机设计的好处。

公开(公告)号：US20050144217A1

公开(公告)日：2005-06-30

申请号：US11062456

申请日：2005-02-22

申请人： Keshab Parhi ,  Jin-Gyun Chung ,  Kwang-Cheol Lee ,  Kyung-Ju Cho

发明人： Keshab Parhi ,  Jin-Gyun Chung ,  Kwang-Cheol Lee ,  Kyung-Ju Cho

IPC分类号： G06F7/499 ,  G06F7/52 ,  G06F7/533 ,  G06F17/50

CPC分类号： G06F7/49947 ,  G06F7/49942 ,  G06F7/5338

摘要： A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. The partial products are accumulated to generate a product (P). To compensate for the quantization error, Booth encoder outputs are used for the generation of error compensation bias. The truncated bits are divided into two groups, a major least significant bit group and a minor least significant bit group, depending upon their effects on the quantization error. Different error compensation methods are applied to each group.

公开(公告)号：US20050166122A1

公开(公告)日：2005-07-28

申请号：US11067631

申请日：2005-02-28

申请人： Keshab Parhi

发明人： Keshab Parhi

IPC分类号： H03M13/09 ,  H03M13/15 ,  H04J3/04 ,  H04L25/03 ,  H03M13/00

CPC分类号： H03M13/091 ,  H03M13/15 ,  H03M13/617 ,  H04J3/047 ,  H04L25/03057

摘要： A K-bit information signal represented by a polynomial U(x) having a degree K−1 is received. The information signal is transformed to form a transformed information signal using a first transform represented by a polynomial G1(x) having a degree P. The transformed information signal is represented by a polynomial T(x) having a degree K+P−1. T(x) equals U(x)G1(x). An initial cyclic code represented by a polynomial R1(x) is generated for the transformed information signal using a second transform represented by a polynomial G2(x), where G2(x) has high-order leading-zero terms. R1(x) equals the remainder obtained by dividing T(x) by G2(x). The initial cyclic code is transformed to form a final cyclic code represented by a polynomial R2(x) using the first transform. R2(x) equals R1(x)/G1(x).

公开(公告)号：US20070014380A1

公开(公告)日：2007-01-18

申请号：US11181347

申请日：2005-07-13

申请人： Yongru Gu ,  Keshab Parhi

发明人： Yongru Gu ,  Keshab Parhi

IPC分类号： H04L25/03

CPC分类号： H04L25/03343 ,  H04L2025/03363

摘要： A method to design parallel TH precoders and a circuit architecture to implement parallel TH precoders have been presented. The parallel design relies on the fact that a TH precoder can be viewed as an IIR filter with an input equal to the sum of the original input to the TH precoder and a compensation signal. The parallel design also relies on the fact that the compensation signal has finite levels. Therefore, precomputation techniques can be applied to calculate intermediate signal values for all possible values of the compensation signal.

摘要翻译： 已经提出了一种设计并行TH预编码器和实现并行TH预编码器的电路架构的方法。 并行设计依赖于以下事实：TH预编码器可被视为具有等于TH预编码器的原始输入和补偿信号之和的输入的IIR滤波器。 并行设计还依赖于补偿信号有限的事实。 因此，可以应用预计算技术来计算补偿信号的所有可能值的中间信号值。

公开(公告)号：US20070014345A1

公开(公告)日：2007-01-18

申请号：US11181348

申请日：2005-07-13

申请人： Yongru Gu ,  Keshab Parhi

发明人： Yongru Gu ,  Keshab Parhi

IPC分类号： H03K5/159 ,  H04L27/00

CPC分类号： H04L25/03343 ,  H03H17/06 ,  H03H2220/04 ,  H04L25/03057

摘要： A method to design low complexity pipelined Tomlinson-Harashima precoders and its associated circuit architectures have been described. The low complexity pipelined TH precoder design relies on the proposed low complexity precomputation based FIR filters. In the low complexity precomputation method for FIR filters, each multiplier is replaced with a multiplexer.

摘要翻译： 已经描述了一种设计低复杂度流水线Tomlinson-Harashima预编码器及其相关电路架构的方法。 低复杂度流水线TH预编码器设计依赖于所提出的低复杂度预计算FIR滤波器。 在FIR滤波器的低复杂度预计算方法中，每个乘法器被替换为多路复用器。

公开(公告)号：US20060197689A1

公开(公告)日：2006-09-07

申请号：US11367041

申请日：2006-03-02

申请人： Jian-Hung Lin ,  Keshab Parhi

发明人： Jian-Hung Lin ,  Keshab Parhi

IPC分类号： H03M7/34

CPC分类号： H03M7/4006

摘要： The invention is directed to techniques of parallelizing binary arithmetic coding. Two exemplary parallelized binary arithmetic coding systems are presented. One parallelized binary arithmetic coding system utilizes linear approximation and a constant probability of a less probable symbol. A second parallelized binary arithmetic coding system utilizes a parallelized table lookup technique. Both parallelized binary arithmetic coding systems may have increased throughput as compared to non-parallelized arithmetic coders.

摘要翻译： 本发明涉及并行化二进制算术编码技术。 提出了两个示例性并行二进制算术编码系统。 一个并行二进制算术编码系统利用线性近似和不太可能的符号的不变概率。 第二并行二进制算术编码系统利用并行表查找技术。 与非并行化算术编码器相比，两个并行二进制算术编码系统可能具有增加的吞吐量。