Patent search ap:("Acorn Technologies Page Inc.") AND inv:"Daniel E. Grupp"

1.

发明授权
Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions 有权

公开(公告)号：US10186592B2

公开(公告)日：2019-01-22

申请号：US15981594

申请日：2018-05-16

Applicant: Acorn Technologies, Inc.

Inventor： Daniel E. Grupp , Daniel J. Connelly

IPC: H01L29/87 , H01L21/28 , H01L29/45 , H01L29/872 , H01L29/16 , H01L29/80 , H01L29/66 , H01L29/161 , H01L29/812 , H01L29/47 , H01L29/08 , H01L21/285 , H01L29/78

Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

2.

发明授权
Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions 有权

公开(公告)号：US10090395B2

公开(公告)日：2018-10-02

申请号：US15877837

申请日：2018-01-23

Applicant: Acorn Technologies, Inc.

Inventor： Daniel E. Grupp , Daniel J. Connelly

IPC: H01L29/78 , H01L29/45 , H01L21/285 , H01L29/08 , H01L29/47 , H01L29/66 , H01L29/812 , H01L29/16 , H01L29/161 , H01L29/872 , H01L29/80

Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

3.

发明授权
Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions 有权

公开(公告)号：US09812542B2

公开(公告)日：2017-11-07

申请号：US15251210

申请日：2016-08-30

Applicant: Acorn Technologies, Inc.

Inventor： Daniel E. Grupp , Daniel J. Connelly

IPC: H01L29/45 , H01L29/78 , H01L21/285 , H01L29/08 , H01L29/47 , H01L29/66 , H01L29/812 , H01L29/16 , H01L29/161 , H01L29/872 , H01L29/80

CPC classification number: H01L29/456 , H01L21/28537 , H01L29/0895 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/45 , H01L29/47 , H01L29/66143 , H01L29/66643 , H01L29/78 , H01L29/7839 , H01L29/785 , H01L29/806 , H01L29/812 , H01L29/872

Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

4.

发明授权
Insulated gate field effect transistor having passivated schottky barriers to the channel 有权
Title translation: 绝缘栅场效应晶体管具有通道的钝化肖特基势垒

公开(公告)号：US09583614B2

公开(公告)日：2017-02-28

申请号：US14298810

申请日：2014-06-06

Applicant: Acorn Technologies, Inc.

Inventor： Daniel E. Grupp , Daniel J. Connelly

IPC: H01L21/338 , H01L29/78 , H01L21/285 , H01L29/08 , H01L29/45 , H01L29/47 , H01L29/49 , H01L29/66 , H01L29/812 , H01L29/786

CPC classification number: H01L29/47 , H01L21/28537 , H01L23/535 , H01L29/0649 , H01L29/0895 , H01L29/456 , H01L29/4908 , H01L29/66143 , H01L29/66636 , H01L29/66643 , H01L29/66666 , H01L29/66772 , H01L29/66795 , H01L29/66848 , H01L29/78 , H01L29/7827 , H01L29/7839 , H01L29/785 , H01L29/78696 , H01L29/812 , H01L29/8126 , Y10S438/958

Abstract: A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

Abstract translation: 具有至少一个通道的钝化肖特基势垒的晶体管包括在p型衬底上的绝缘栅极结构，其中沟道位于绝缘栅极结构之下。通道和绝缘栅极结构分别限定了从绝缘栅极结构的第一和第二侧分别延伸到绝缘栅极结构下方朝向沟道的第一和第二底切空隙区域。钝化层包括在通道的至少一个暴露的侧壁表面上，并且金属源极和漏极端子位于通道的相应的第一和第二侧上，包括在钝化层上以及绝缘栅极结构下方的底切空隙区域内。金属源极和漏极端子中的至少一个包括在p型衬底的价带附近具有功函数的金属。

5.

发明授权
Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions 有权
Title translation: 在电连接处去除半导体的费米能级的方法以及包含这种结的装置的方法

公开(公告)号：US09209261B2

公开(公告)日：2015-12-08

申请号：US14743916

申请日：2015-06-18

Applicant: Acorn Technologies, Inc.

Inventor： Daniel E. Grupp , Daniel J. Connelly

IPC: H01L29/66 , H01L21/82 , H01L29/45 , H01L29/16 , H01L29/161 , H01L29/47 , H01L29/78 , H01L29/08

CPC classification number: H01L29/456 , H01L21/28537 , H01L29/0895 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/45 , H01L29/47 , H01L29/66143 , H01L29/66643 , H01L29/78 , H01L29/7839 , H01L29/785 , H01L29/806 , H01L29/812 , H01L29/872

Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Abstract translation: 一种电气装置，其中界面层设置在导体和半导体之间并与导体和半导体接触。

6.

发明申请
METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS 有权
Title translation: 用于识别电气连接处的半导体的FERMI电平的方法和包含这种结点的器件

公开(公告)号：US20150287800A1

公开(公告)日：2015-10-08

申请号：US14743916

申请日：2015-06-18

Applicant: Acorn Technologies, Inc.

Inventor： Daniel E. Grupp , Daniel J. Connelly

IPC: H01L29/45 , H01L29/08 , H01L29/47 , H01L29/78 , H01L29/16 , H01L29/161

CPC classification number: H01L29/456 , H01L21/28537 , H01L29/0895 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/45 , H01L29/47 , H01L29/66143 , H01L29/66643 , H01L29/78 , H01L29/7839 , H01L29/785 , H01L29/806 , H01L29/812 , H01L29/872

Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Abstract translation: 一种电气装置，其中界面层设置在导体和半导体之间并与导体和半导体接触。

7.

发明授权
Insulated gate field effect transistor having passivated schottky barriers to the channel 有权
Title translation: 绝缘栅场效应晶体管具有通道的钝化肖特基势垒

公开(公告)号：US08916437B2

公开(公告)日：2014-12-23

申请号：US13757597

申请日：2013-02-01

Applicant: Acorn Technologies, Inc.

Inventor： Daniel E. Grupp , Daniel J. Connelly

IPC: H01L29/66 , H01L29/78 , H01L29/49 , H01L29/812 , H01L29/45 , H01L29/47 , H01L29/08 , H01L21/285 , H01L29/786

CPC classification number: H01L29/47 , H01L21/28537 , H01L23/535 , H01L29/0649 , H01L29/0895 , H01L29/456 , H01L29/4908 , H01L29/66143 , H01L29/66636 , H01L29/66643 , H01L29/66666 , H01L29/66772 , H01L29/66795 , H01L29/66848 , H01L29/78 , H01L29/7827 , H01L29/7839 , H01L29/785 , H01L29/78696 , H01L29/812 , H01L29/8126 , Y10S438/958

Abstract: A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel, and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

Abstract translation: 具有至少一个通道的钝化肖特基势垒的晶体管包括在p型衬底上的绝缘栅极结构，其中沟道位于绝缘栅极结构之下。通道和绝缘栅极结构分别限定了从绝缘栅极结构的第一和第二侧分别延伸到绝缘栅极结构下方朝向沟道的第一和第二底切空隙区域。钝化层包括在通道的至少一个暴露的侧壁表面上，并且金属源极和漏极端子位于通道的相应的第一和第二侧上，包括在钝化层上以及绝缘栅极结构下面的底切空隙区域。金属源极和漏极端子中的至少一个包括在p型衬底的价带附近具有功函数的金属。