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    Method of routing a design to increase the quality of the design
    3.
    发明授权
    Method of routing a design to increase the quality of the design 有权
    路由设计方法以提高设计质量

    公开(公告)号：US07367007B1

    公开(公告)日：2008-04-29

    申请号：US11170408

    申请日：2005-06-29

    申请人： Prasanna Sundararajan ,  Carter Hamilton ,  Ian L. McEwen

    发明人： Prasanna Sundararajan ,  Carter Hamilton ,  Ian L. McEwen

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： A method of circuit design for a programmable logic device (PLD) can include identifying a plurality of routing resources, wherein each of the plurality of routing resources is associated with a reliability measure, and selecting routing resources for use in routing a circuit design for the PLD according to, at least in part, the reliability measures. The circuit design for the PLD can be routed using the selected routing resources.

    摘要翻译： 用于可编程逻辑器件（PLD）的电路设计方法可以包括识别多个路由资源，其中多个路由资源中的每一个与可靠性度量相关联，并且选择路由资源用于路由电路设计 至少部分依据PLD的可靠性措施。 PLD的电路设计可以使用选定的路由资源进行路由。

    Methods of reducing the susceptibility of PLD designs to single event upsets
    4.
    发明授权
    Methods of reducing the susceptibility of PLD designs to single event upsets 有权
    降低PLD设计对单次事件的敏感性的方法

    公开(公告)号：US07111215B1

    公开(公告)日：2006-09-19

    申请号：US10768304

    申请日：2004-01-29

    申请人： Eric R. Keller ,  Prasanna Sundararajan ,  Stephen M. Trimberger

    发明人： Eric R. Keller ,  Prasanna Sundararajan ,  Stephen M. Trimberger

    IPC分类号： G01R31/28

    CPC分类号： H03K19/00392 ,  G11C5/063 ,  G11C11/4125 ,  H03K19/17736 ,  H03K19/17764

    摘要： Methods of implementing designs in programmable logic devices (PLDs) to reduce susceptibility to single-event upsets (SEUs) by taking advantage of the fact that most PLD designs leave many routing resources unused. The unused routing resources can be used to provide duplicate routing paths between source and destination of signals in the design. The duplicate paths are selected such that an SEU affecting one of the duplicate paths simply switches the signal between the two paths. Thus, if one path is disabled due to an SEU, the other path can still provide the necessary connection, and the functionality of the design is unaffected. The methods can be applied, for example, to routing software for field programmable gate arrays (FPGAs) having programmable routing multiplexers controlled by static RAM-based configuration memory cells.

    摘要翻译： 通过利用大多数PLD设计留下许多路由资源的事实，在可编程逻辑器件（PLD）中实现设计的方法以减少对单事件异常（SEU）的敏感性。 未使用的路由资源可用于在设计中的信号的源和目的地之间提供重复的路由路径。 选择重复路径使得影响一个重复路径的SEU简单地在两个路径之间切换信号。 因此，如果由于SEU而使一个路径被禁用，则另一个路径仍然可以提供必要的连接，并且设计的功能不受影响。 该方法可以应用于例如具有由基于静态RAM的配置存储器单元控制的可编程路由多路复用器的现场可编程门阵列（FPGA）的路由软件。

    Run-time reconfigurable testing of programmable logic devices
    5.
    发明授权
    Run-time reconfigurable testing of programmable logic devices 有权
    可编程逻辑器件的运行时可重构测试

    公开(公告)号：US06668237B1

    公开(公告)日：2003-12-23

    申请号：US10052720

    申请日：2002-01-17

    申请人： Steven A. Guccione ,  Prasanna Sundararajan ,  Scott P. McMillan

    发明人： Steven A. Guccione ,  Prasanna Sundararajan ,  Scott P. McMillan

    IPC分类号： G01R2728

    CPC分类号： G01R31/318516

    摘要： Method and system for testing circuitry of a programmable logic device (PLD). A host data processing arrangement is configured with a run-time reconfiguration programming interface, and a run-time reconfiguration test program that invokes methods of the interface executes on the host arrangement. In response to a method of the programming interface invoked from the test program, the PLD is configured with a first configuration bitstream. State data are then read back from the PLD in response to a method of the programming interface invoked from the test program. The test program also identifies differences between the state data and expected-results data.

    摘要翻译： 用于测试可编程逻辑器件（PLD）电路的方法和系统。 主机数据处理装置配置有运行时重配置编程接口，并且在主机装置上执行调用接口的方法的运行时重配置测试程序。 响应于从测试程序调用的编程接口的方法，PLD配置有第一配置比特流。 响应于从测试程序调用的编程接口的方法，从PLD读回状态数据。 测试程序还识别状态数据和预期结果数据之间的差异。

    Method and apparatus for tolerating defects in a programmable logic device using runtime parameterizable cores
    6.
    发明授权
    Method and apparatus for tolerating defects in a programmable logic device using runtime parameterizable cores 有权
    用于使用运行时可参数化的内核来容忍可编程逻辑器件中的缺陷的方法和装置

    公开(公告)号：US06530071B1

    公开(公告)日：2003-03-04

    申请号：US09676298

    申请日：2000-09-28

    申请人： Steven A. Guccione ,  Prasanna Sundararajan

    发明人： Steven A. Guccione ,  Prasanna Sundararajan

    IPC分类号： G06F1750

    CPC分类号： G06F11/142 ,  G06F17/5054

    摘要： Method and apparatus for tolerating defects in a programmable logic device (PLD). A PLD includes a plurality of configurable logic elements and interconnect resources, wherein one or more of the configurable logic elements and interconnect resources have circuit defects. A design program is executed that is suitable for run-time reconfiguration of the PLD. The design program includes executable code that specifies a circuit design and generates a configuration bitstream that implements the circuit design on the programmable logic device. The design program also includes code that selectively skips the configurable logic elements and interconnect resources that contain the defects. In various embodiments, an individual configurable logic element, an entire row, or an entire column of elements can be skipped responsive to an input parameter.

    摘要翻译： 用于容许可编程逻辑器件（PLD）中的缺陷的方法和装置。 PLD包括多个可配置逻辑元件和互连资源，其中一个或多个可配置逻辑元件和互连资源具有电路缺陷。 执行适合PLD的运行时重新配置的设计程序。 设计程序包括指定电路设计的可执行代码，并生成在可编程逻辑器件上实现电路设计的配置位流。 设计程序还包括有选择地跳过可配置逻辑元件并互连包含缺陷的资源的代码。 在各种实施例中，可以响应于输入参数跳过单个可配置逻辑元件，整行或整列元素。

    Bootable programmable logic device for internal decoding of encoded configuration data
    8.
    发明授权
    Bootable programmable logic device for internal decoding of encoded configuration data 有权
    可引导可编程逻辑器件，用于编码配置数据的内部解码

    公开(公告)号：US07328335B1

    公开(公告)日：2008-02-05

    申请号：US10956989

    申请日：2004-10-01

    申请人： Prasanna Sundararajan ,  Brandon J. Blodget ,  Scott P. McMillan ,  Philip B. James-Roxby ,  Eric R. Keller

    发明人： Prasanna Sundararajan ,  Brandon J. Blodget ,  Scott P. McMillan ,  Philip B. James-Roxby ,  Eric R. Keller

    IPC分类号： G06F9/24

    CPC分类号： H03K19/17748 ,  G06F15/7867 ,  H03K19/17732 ,  H03K19/17768

    摘要： Method and apparatus for decoding configuration data is described. A programmable logic device having a configuration interface is coupled to boot memory coupled at the configuration interface. The boot memory contains boot cores for configuring the programmable logic device via the configuration interface. The boot cores include a configuration decoder core and an internal processor interface core. The boot cores may further include a processor core. The configuration decoder core provides a peripheral interface internal to the programmable logic device, and the boot memory contains at least one set of instructions for decoding encoded data and at least one library for writing decoded encoded data to configuration memory of the programmable logic device. The encoded data is obtained from data memory via the peripheral interface.

    摘要翻译： 描述用于解码配置数据的方法和装置。 具有配置接口的可编程逻辑器件耦合到在配置接口耦合的引导存储器。 引导内存包含用于通过配置界面配置可编程逻辑器件的引导内核。 引导核心包括配置解码器核心和内部处理器接口核心。 引导核心可以进一步包括处理器核心。 配置解码器核心提供可编程逻辑器件内部的外围接口，并且引导存储器包含用于解码编码数据的至少一组指令和用于将解码的编码数据写入可编程逻辑器件的配置存储器的至少一个存储库。 编码数据经由外围接口从数据存储器获得。

    Adaptable configuration interface for a programmable logic device
    9.
    发明授权
    Adaptable configuration interface for a programmable logic device 有权
    适用于可编程逻辑器件的配置界面

    公开(公告)号：US06665766B1

    公开(公告)日：2003-12-16

    申请号：US09639513

    申请日：2000-08-14

    申请人： Steven A. Guccione ,  Prasanna Sundararajan

    发明人： Steven A. Guccione ,  Prasanna Sundararajan

    IPC分类号： G06F1314

    CPC分类号： G06F17/5054

    摘要： An adaptable configuration interface for a programmable logic device (PLD). A PLD includes a plurality of configuration pins and circuitry implementing read and write protocols for reading data from and writing configuration data to the PLD. A register that is external to the PLD is connected to the configuration pins of the PLD, and a processor is coupled to the register. A first set of routines, each executable on the processor, are configured to read and write values from and to the register. A second set of routines, each executable on the processor, provide an application programming interface for the configuration and readback of data from the PLD via the first set of routines. The layered structure of the interface routines aids in incrementally changing from a software controlled configuration interface to an interface that is a combination of hardware and software.

    摘要翻译： 适用于可编程逻辑器件（PLD）的配置界面。 PLD包括多个配置引脚和实现用于从PLD读取数据和向PLD写入配置数据的读和写协议的电路。 PLD外部的寄存器连接到PLD的配置引脚，处理器连接到寄存器。 处理器上的每个可执行程序的第一组程序被配置为从寄存器读取和写入值。 第二组程序，每个可执行的处理器，提供一个应用程序编程接口，用于通过第一组例程从PLD配置和读回数据。 接口例程的分层结构有助于从软件控制的配置接口逐渐改变为作为硬件和软件组合的接口。

    Compiler directed cache coherence for many caches generated from high-level language source code
    10.
    发明授权
    Compiler directed cache coherence for many caches generated from high-level language source code 有权
    针对高级语言源代码生成的许多缓存的编译器定向缓存一致性

    公开(公告)号：US09378003B1

    公开(公告)日：2016-06-28

    申请号：US12508437

    申请日：2009-07-23

    申请人： Prasanna Sundararajan ,  Andrew R. Putnam ,  Jeffrey M. Mason

    发明人： Prasanna Sundararajan ,  Andrew R. Putnam ,  Jeffrey M. Mason

    IPC分类号： G06F9/45

    CPC分类号： G06F8/4441 ,  G06F8/443 ,  G06F8/4442 ,  G06F8/452 ,  G06F8/454 ,  G06F8/456

    摘要： Approaches for generating and operating an electronic system. High-level language (HLL) source code is compiled into equivalent intermediate language program code. The compilation determines a plurality of caches for storing data referenced by the HLL source. Flush instructions are inserted in the intermediate language program. Each flush instruction references one of caches and is inserted in the intermediate language program immediately following an instruction that is last to write to that cache. The intermediate language program is translated into a hardware description that specifies the plurality of caches, circuits for processing data in the caches, and for each of the caches a flush interface that initiates writing data from the cache to a main memory in response to a flush signal. The timing of the respective flush signal is determined based on placement of one of the one or more flush instructions in the intermediate language program.

    摘要翻译： 生成和操作电子系统的方法。 高级语言（HLL）源代码被编译成等效的中间语言程序代码。 编译确定用于存储由HLL源引用的数据的多个高速缓存。 刷新指令插入中间语言程序。 每个刷新指令引用一个缓存，并且在紧跟在最后写入该缓存的指令之后插入到中间语言程序中。 中间语言程序被转换为指定多个高速缓存的硬件描述，用于处理高速缓存中的数据的电路，以及用于每个高速缓存的闪存接口，其响应于刷新而启动从高速缓存向主存储器写入数据 信号。 基于中间语言程序中的一个或多个刷新指令中的一个的布置来确定各个刷新信号的定时。