公开(公告)号：US06892296B2

公开(公告)日：2005-05-10

申请号：US09773473

申请日：2001-02-01

申请人： Adrian P. Wise ,  Kevin Boyd ,  Anothy Peter Claydon ,  William P. Robbins ,  Helen R. Finch ,  Martin W. Sotheran ,  Anthony Mark Jones

发明人： Adrian P. Wise ,  Kevin Boyd ,  Anothy Peter Claydon ,  William P. Robbins ,  Helen R. Finch ,  Martin W. Sotheran ,  Anthony Mark Jones

IPC分类号： G06F7/00 ,  G06F9/38 ,  G06F9/44 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F13/16 ,  G06F13/28 ,  G06T9/00 ,  H04N7/26 ,  H04N7/50 ,  G06F15/00 ,  G06F7/08 ,  G06F7/24 ,  G06F7/36

CPC分类号： G06F9/3867 ,  G06F9/4494 ,  G06F12/0207 ,  G06F12/04 ,  G06F12/0607 ,  G06F13/16 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/28 ,  H04N19/13 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N19/91

摘要： A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number. A token decode circuit positioned in certain of the stages recognizes certain of the tokens as control tokens pertinent to that stage and passes unrecognized control tokens to a succeeding stage. A reconfigurable decode and parser processing means positioned in certain of the stages is responsive to a recognized control token and reconfigures a particular stage to handle an identified data token. Methods relating to the decoder and decompression system include processing steps relating thereto.

摘要翻译： 流水线视频解码器和解压缩系统处理多个单独编码的比特流，其被布置为数字比特的单个串行比特流，并且具有单独编码的控制码对和串行比特流中携带的对应数据。 流水线系统采用多个互连的级来解码和解压缩单个比特流，包括起始码检测器。 当处于搜索模式时，起始代码检测器搜索与多个压缩标准之一相对应的特定开始代码。 响应于单个串行比特流的起始码检测器产生控制令牌和数据令牌。 相应的令牌包括多个数据字。 每个数据字具有指示其中存在附加字的扩展位。 因此数据字数量无限。 定位在某些阶段的令牌解码电路将某些令牌识别为与该级相关的控制令牌，并将未被识别的控制令牌传递到后续级。 定位在某些阶段的可重构解码和解析器处理装置响应于识别的控制令牌，并且重新配置特定级以处理所识别的数据令牌。 与解码器和解压缩系统相关的方法包括与其相关的处理步骤。

公开(公告)号：US06910125B2

公开(公告)日：2005-06-21

申请号：US09777283

申请日：2001-02-06

申请人： Adrian P. Wise ,  Martin W. Sotheran ,  William P. Robbins ,  Anthony M. Jones ,  Anthony Peter John Claydon ,  Kevin Boyd ,  Helen R. Finch

发明人： Adrian P. Wise ,  Martin W. Sotheran ,  William P. Robbins ,  Anthony M. Jones ,  Anthony Peter John Claydon ,  Kevin Boyd ,  Helen R. Finch

IPC分类号： G06F7/00 ,  G06F9/38 ,  G06F9/44 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F13/16 ,  G06F13/28 ,  G06T9/00 ,  H04N7/26 ,  H04N7/50 ,  G06F15/00 ,  G06F7/08 ,  G06F7/24 ,  G06F7/36

CPC分类号： G06F9/3867 ,  G06F9/4494 ,  G06F12/0207 ,  G06F12/04 ,  G06F12/0607 ,  G06F13/16 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/28 ,  H04N19/13 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N19/91

摘要： A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number. A token decode circuit positioned in certain of the stages recognizes certain of the tokens as control tokens pertinent to that stage and passes unrecognized control tokens to a succeeding stage. A reconfigurable decode and parser processing means positioned in certain of the stages is responsive to a recognized control token and reconfigures a particular stage to handle an identified data token. Methods relating to the decoder and decompression system include processing steps relating thereto.

摘要翻译： 流水线视频解码器和解压缩系统处理多个单独编码的比特流，其被布置为数字比特的单个串行比特流，并且具有单独编码的控制码对和串行比特流中携带的对应数据。 流水线系统采用多个互连的级来解码和解压缩单个比特流，包括起始码检测器。 当处于搜索模式时，起始代码检测器搜索与多个压缩标准之一相对应的特定开始代码。 响应于单个串行比特流的起始码检测器产生控制令牌和数据令牌。 相应的令牌包括多个数据字。 每个数据字具有指示其中存在附加字的扩展位。 因此数据字数量无限。 定位在某些阶段的令牌解码电路将某些令牌识别为与该级相关的控制令牌，并将未被识别的控制令牌传递到后续级。 定位在某些阶段的可重构解码和解析器处理装置响应于识别的控制令牌，并且重新配置特定级以处理所识别的数据令牌。 与解码器和解压缩系统相关的方法包括与其相关的处理步骤。

公开(公告)号：US6067417A

公开(公告)日：2000-05-23

申请号：US946754

申请日：1997-10-07

申请人： Adrian P. Wise ,  Martin W Sotheran ,  William P. Robbins

发明人： Adrian P. Wise ,  Martin W Sotheran ,  William P. Robbins

IPC分类号： G06F9/38 ,  G06F9/44 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F13/16 ,  G06F13/28 ,  G06T9/00 ,  H04N7/26 ,  H04N7/50 ,  G06F15/82

CPC分类号： G06F12/0207 ,  G06F12/04 ,  G06F12/0607 ,  G06F13/16 ,  G06F13/28 ,  G06F9/3867 ,  G06F9/4436 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N19/91

摘要： A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

摘要翻译： 多标准视频解压缩装置具有通过布置为流水线处理机的两线接口互连的多个级。 控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。 令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。 重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。 公开了各种独特的支持子系统电路和处理技术来实现该系统。

公开(公告)号：US06263422B1

公开(公告)日：2001-07-17

申请号：US08484730

申请日：1995-06-07

申请人： Adrian P. Wise ,  Martin W. Sotheran ,  William P. Robbins

发明人： Adrian P. Wise ,  Martin W. Sotheran ,  William P. Robbins

IPC分类号： G06F930

CPC分类号： G06F9/3867 ,  G06F9/4494 ,  G06F12/0207 ,  G06F12/04 ,  G06F12/0607 ,  G06F13/16 ,  G06F13/28 ,  H04N19/13 ,  H04N19/42 ,  H04N19/423 ,  H04N19/44 ,  H04N19/61 ,  H04N19/91

摘要： A plurality of processing stages interposed between an input and an output of a system including a pipeline machine interconnect for conveyance of tokens along the pipeline. Control and or data tokens in the form of universal adaptation units interface with all of the stages in the pipeline and alternatively interact with selected stages in the pipeline so that the processing stages in the pipeline are afforded enhanced flexibility in configuration and processing. In one embodiment of the system, the stages accept a data stream having portions encoded according to respectively different video formats. At least one of the stages includes circuitry for generating signals to indicate an end-of-picture data decoding. The stage includes state machine logic that is responsive to the generated signals for effecting an end of picture data decoding by clearing the pipeline. A method of clearing the pipeline includes receiving a data stream, indicating an end of picture data decoding, and clearing the pipeline when an end of picture data decoding has been indicated.

摘要翻译： 多个处理台，其插入在包括管道机器互连的系统的输入和输出之间，用于沿管道输送令牌。 以通用适配单元形式的控制和/或数据令牌与流水线中的所有阶段接口，并且交替地与流水线中的选定阶段进行交互，从而提供流水线处理阶段在配置和处理方面的增强灵活性。 在系统的一个实施例中，阶段接受具有根据分别不同的视频格式编码的部分的数据流。 至少一个级包括用于产生信号以指示画面结束数据解码的电路。 舞台包括响应于所产生的信号的状态机逻辑，以通过清除流水线来实现图像数据解码的结束。 清除流水线的方法包括：当已经指示图像数据解码结束时，接收指示图像数据解码结束的数据流，以及清除流水线。

公开(公告)号：US06330665B1

公开(公告)日：2001-12-11

申请号：US08992859

申请日：1997-12-10

申请人： Adrian P. Wise ,  Kevin J. Boyd ,  Helen R Finch ,  William P Robbins

发明人： Adrian P. Wise ,  Kevin J. Boyd ,  Helen R Finch ,  William P Robbins

IPC分类号： G06F700

CPC分类号： G06F12/0207 ,  G06F9/3867 ,  G06F9/4494 ,  G06F12/04 ,  G06F13/16 ,  G06F13/28 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N19/91

摘要： A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

摘要翻译： 多标准视频解压缩装置具有通过布置为流水线处理机的两线接口互连的多个级。 控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。 令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。 重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。 公开了各种独特的支持子系统电路和处理技术来实现该系统。

公开(公告)号：US5835792A

公开(公告)日：1998-11-10

申请号：US487134

申请日：1995-06-07

申请人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

发明人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

IPC分类号： H04N5/92 ,  G06F3/14 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F12/08 ,  G06F13/00 ,  G06F13/16 ,  G06F13/28 ,  G06F13/37 ,  G06T9/00 ,  G11B7/00 ,  G11B27/10 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L7/00 ,  H04L7/08 ,  H04L12/433 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50 ,  H04N7/52

CPC分类号： H04N21/4307 ,  G06F12/0207 ,  G06F13/16 ,  G06F13/28 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N21/4305 ,  H04N21/44004 ,  G06F12/04 ,  H04N19/13 ,  H04N19/91

摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

公开(公告)号：US5829007A

公开(公告)日：1998-10-27

申请号：US486908

申请日：1995-06-07

申请人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

发明人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

IPC分类号： H04N5/92 ,  G06F3/14 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F12/08 ,  G06F13/00 ,  G06F13/16 ,  G06F13/28 ,  G06F13/37 ,  G06T9/00 ,  G11B7/00 ,  G11B27/10 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L7/00 ,  H04L7/08 ,  H04L12/433 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50 ,  H04N7/52

CPC分类号： H04N21/4307 ,  G06F12/0207 ,  G06F13/16 ,  G06F13/28 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N21/4305 ,  H04N21/44004 ,  G06F12/04 ,  H04N19/13 ,  H04N19/91

摘要： A RAM implementation of asynchronous swing buffering is provided in which two buffers are operated asynchronously; one is written while the other is read. Accordingly, this allows for a data stream having a fast rate of through-put to be resynchronized to another rate, while still maintaining a desired rate. In the invention, the write control and read control both have state indicators for communicating which buffer they are using and whether the controls are waiting for access or are, in fact, accessing that buffer.

摘要翻译： 提供了异步摆动缓冲的RAM实现，其中两个缓冲器是异步操作的; 一个是写在另一个被读取。 因此，这允许具有快速吞吐速率的数据流与另一个速率重新同步，同时仍然保持期望的速率。 在本发明中，写入控制和读取控制都具有用于通信它们正在使用哪个缓冲器的状态指示符，以及控制是否正在等待访问，或实际上访问该缓冲器。

公开(公告)号：US5768629A

公开(公告)日：1998-06-16

申请号：US479910

申请日：1995-06-07

申请人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

发明人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

IPC分类号： H04N5/92 ,  G06F3/14 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F12/08 ,  G06F13/00 ,  G06F13/16 ,  G06F13/28 ,  G06F13/37 ,  G06T9/00 ,  G11B7/00 ,  G11B27/10 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L7/00 ,  H04L7/08 ,  H04L12/433 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50 ,  H04N7/52

CPC分类号： H04N21/4307 ,  G06F12/0207 ,  G06F13/16 ,  G06F13/28 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N21/4305 ,  H04N21/44004 ,  G06F12/04 ,  H04N19/13 ,  H04N19/91

摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

摘要翻译： 一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。 控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。 令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。 重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。 公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等 。

公开(公告)号：US5821885A

公开(公告)日：1998-10-13

申请号：US473813

申请日：1995-06-07

申请人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

发明人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

IPC分类号： H04N5/92 ,  G06F3/14 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F12/08 ,  G06F13/00 ,  G06F13/16 ,  G06F13/28 ,  G06F13/37 ,  G06T9/00 ,  G11B7/00 ,  G11B27/10 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L7/00 ,  H04L7/08 ,  H04L12/433 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50 ,  H04N7/52

CPC分类号： H04N21/4307 ,  G06F12/0207 ,  G06F13/16 ,  G06F13/28 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N21/4305 ,  H04N21/44004 ,  G06F12/04 ,  H04N19/13 ,  H04N19/91

摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

公开(公告)号：US5740460A

公开(公告)日：1998-04-14

申请号：US481772

申请日：1995-06-07

申请人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

发明人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

IPC分类号： H04N5/92 ,  G06F3/14 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F12/08 ,  G06F13/00 ,  G06F13/16 ,  G06F13/28 ,  G06F13/37 ,  G06T9/00 ,  G11B7/00 ,  G11B27/10 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L7/00 ,  H04L7/08 ,  H04L12/433 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50 ,  H04N7/52 ,  G06F15/66

CPC分类号： H04N21/4307 ,  G06F12/0207 ,  G06F13/16 ,  G06F13/28 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N21/4305 ,  H04N21/44004 ,  G06F12/04 ,  H04N19/13 ,  H04N19/91

摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

摘要翻译： 一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。 控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。 令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。 重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。 公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等 。