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公开(公告)号：US20230206995A1
公开(公告)日：2023-06-29
申请号：US17564680
申请日：2021-12-29
IPC分类号： G11C11/4099 , G11C11/4076 , G11C11/408 , G11C11/4094 , G11C11/4074 , G11C11/4096
CPC分类号： G11C11/4099 , G11C11/4076 , G11C11/4085 , G11C11/4094 , G11C11/4074 , G11C11/4096
摘要： A system and method for efficiently resetting data stored in a memory array are described. In various implementations, an integrated circuit includes a memory for storing data, and a processing unit that generates access requests for the data stored in the memory. When access circuitry of the memory array begins a reset operation, it reduces a power supply voltage level used by memory bit cells in a column of the array to a value less than a threshold voltage of transistors. Therefore, the p-type transistors of the bit cells do not contend with the write driver during a write operation. The access circuitry provides the reset data on the write bit lines, and asserts each of the write word lines of the memory array. To complete the write operation, the access circuitry returns the power supply voltage level from below the threshold voltage level to an operating voltage level.
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公开(公告)号：US20210407617A1
公开(公告)日：2021-12-30
申请号：US17027983
申请日：2020-09-22
发明人： Russell Schreiber , Keith A. Kasprak , Vance Threatt , James A. Wingfield , William A. Halliday , Srinivas R. Sathu , Arijit Banerjee
IPC分类号： G11C29/44 , G11C29/12 , G11C7/12 , G06F12/0811
摘要： An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.
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公开(公告)号：US20180226111A1
公开(公告)日：2018-08-09
申请号：US15424418
申请日：2017-02-03
发明人： Alexander W. Schaefer , Ravi T. Jotwani , Samiul Haque Khan , David Hugh McIntyre , Stephen Victor Kosonocky , John J. Wuu , Russell Schreiber
CPC分类号： G11C8/08 , G11C5/145 , G11C11/413 , G11C11/418 , G11C11/419
摘要： A system and method for efficient power, performance and stability tradeoffs of memory accesses under a variety of conditions are described. A system management unit in a computing system interfaces with a memory and a processing unit, and uses boosting of word line voltage levels in the memory to assist write operations. The computing system supports selecting one of multiple word line boost values, each with an associated cross-over region. A cross-over region is a range of operating voltages for the memory used for determining whether to enable or disable boosting of word line voltage levels in the memory. The system management unit selects between enabling and disabling the boosting of word line voltage levels based on a target operational voltage for the memory and the cross-over region prior to updating the operating parameters of the memory to include the target operational voltage.
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4.发明申请TECHNIQUES AND CIRCUITS FOR TESTING A VIRTUAL POWER SUPPLY AT AN INTEGRATED CIRCUIT DEVICE 有权在集成电路设备中测试虚拟电源的技术和电路公开(公告)号：US20150022218A1
公开(公告)日：2015-01-22
申请号：US13946107
申请日：2013-07-19
发明人： Russell Schreiber , Joel Irby , Sudha Thiruvengadam , Carl Dietz
IPC分类号： G01R31/02
CPC分类号： G01R31/2884
摘要： A power grid provides power to one or more modules of an integrated circuit device via a virtual power supply signal. A test module is configured to respond to assertion of a test signal so that, when the power grid is working properly and is not power gated, an output of the test module matches the virtual power supply. When the power grid is not working properly, the output of the test module is a fixed logic signal that does not vary based on the power gated state of the one or more modules.
摘要翻译： 电力网通过虚拟电源信号向集成电路装置的一个或多个模块供电。 测试模块被配置为响应测试信号的断言，使得当电网正常工作并且不是电源门控时，测试模块的输出与虚拟电源匹配。 当电网不能正常工作时，测试模块的输出是固定的逻辑信号，它不会根据一个或多个模块的电源门控状态而变化。
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公开(公告)号：US11929114B2
公开(公告)日：2024-03-12
申请号：US17564680
申请日：2021-12-29
IPC分类号： G11C11/4074 , G11C11/4076 , G11C11/408 , G11C11/4094 , G11C11/4096 , G11C11/4099
CPC分类号： G11C11/4099 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4094 , G11C11/4096
摘要： A system and method for efficiently resetting data stored in a memory array are described. In various implementations, an integrated circuit includes a memory for storing data, and a processing unit that generates access requests for the data stored in the memory. When access circuitry of the memory array begins a reset operation, it reduces a power supply voltage level used by memory bit cells in a column of the array to a value less than a threshold voltage of transistors. Therefore, the p-type transistors of the bit cells do not contend with the write driver during a write operation. The access circuitry provides the reset data on the write bit lines, and asserts each of the write word lines of the memory array. To complete the write operation, the access circuitry returns the power supply voltage level from below the threshold voltage level to an operating voltage level.
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公开(公告)号：US11356093B2
公开(公告)日：2022-06-07
申请号：US16817976
申请日：2020-03-13
发明人： Russell Schreiber
IPC分类号： H03K19/00 , H03K19/0175 , H04L25/20
摘要： An electronic device includes a die stack having a plurality of die. The die stack includes a die parity path spanning the plurality of die and configured to alternatingly identify each die as a first type or a second type. The die stack further includes an inter-die signal path spanning the plurality of die and configured to propagate an inter-die signal through the plurality of die, wherein the inter-die signal path is configured to invert a logic state of the inter-die signal between each die. Each die of the plurality of die includes signal formatting logic configured to selectively invert a logic state of the inter-die signal before providing it to other circuitry of the die responsive to whether the die is designated as the first type or the second type.
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公开(公告)号：US20210035614A1
公开(公告)日：2021-02-04
申请号：US16820828
申请日：2020-03-17
发明人： Russell Schreiber
IPC分类号： G11C5/14 , G11C11/412 , G11C11/419 , G11C11/418
摘要： An integrated circuit includes a memory and a system management unit. The memory has a memory array operating according to a memory power supply voltage and access circuitry coupled to said memory array operating according to a logic power supply voltage. The system management unit activates a first control signal to control an operation of the memory selectively in response to a magnitude of a difference in voltage between the logic power supply voltage and the memory power supply voltage.
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公开(公告)号：US10303398B2
公开(公告)日：2019-05-28
申请号：US15794457
申请日：2017-10-26
IPC分类号： G11C5/06 , G06F3/06 , G06F12/1009
摘要： A processing system includes a compute die and a stacked memory stacked with the compute die. The stacked memory includes a first memory die and a second memory die stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.
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公开(公告)号：US20180364781A1
公开(公告)日：2018-12-20
申请号：US15626847
申请日：2017-06-19
发明人： Russell Schreiber
CPC分类号： G06F1/324 , G06F1/3287 , G06F1/3296 , H03K5/159
摘要： A system and method for providing efficient clock gating capability for functional units are described. A functional unit uses a clock gating circuit for power management. A setup time of a single device propagation delay is provided for a received enable signal. When each of a clock signal, the enable signal and a delayed clock signal is asserted, an evaluate node of the clock gating circuit is discharged. When each of the clock signal and a second clock signal is asserted and the enable signal is negated, the evaluate node is left floating for a duration equal to the hold time. Afterward, the devices in a delayed onset keeper are turned on and the evaluate node has a path to the power supply. When the clock signal is negated, the evaluate node is precharged.
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公开(公告)号：US10043572B1
公开(公告)日：2018-08-07
申请号：US15663096
申请日：2017-07-28
发明人： Russell Schreiber , John J. Wuu , Keith Kasprak
IPC分类号： G11C11/40 , G11C11/419 , G11C11/418 , G11C5/14 , G11C5/06
摘要： A system and method for providing efficient power, performance and stability tradeoffs of memory accesses are described. A computing system uses a memory for storing data, and a processing unit, which generates access request. The memory stores data and includes a dummy cell between a first region and a second region. The first region and the second region operate with at least one of two operating states such as an awake state and a sleep state. The dummy cell uses two ground connections to support two separate ground references. In one example, a first ground reference is zero volts and a second ground reference is a floating node. In another example, the first ground reference is a value shared by one of the two regions and the second ground reference is the floating node.
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