公开(公告)号：US09183673B2

公开(公告)日：2015-11-10

申请号：US13705667

申请日：2012-12-05

申请人： Ai Omodaka ,  Yoshiyuki Shioyama ,  Kenji Kawabata

发明人： Ai Omodaka ,  Yoshiyuki Shioyama ,  Kenji Kawabata

IPC分类号： G06F9/455 ,  G06F11/22 ,  G06T17/10 ,  G06F17/50

CPC分类号： G06T17/10 ,  G06F17/5009

摘要： In accordance with an embodiment, a simulation apparatus includes a two-dimensional section dividing processing unit, a two-dimensional simulator, a one-dimensional combining processing unit, and a three-dimensional shape combining processing unit. The two-dimensional section dividing processing unit divides a three-dimensional shape as a simulation target into at least one set of two-dimensional sections intersecting with each other and defines the three-dimensional shape as the two-dimensional sections. The two-dimensional simulator runs a two-dimensional shape simulation in each time step for each of the two-dimensional sections obtained by the dividing and acquires a two-dimensional shape. The one-dimensional combining processing unit extracts a film configuration for each intersection of the two-dimensional sections from the acquired two-dimensional shape and combines the film configurations to acquire one-dimensional film configurations. The three-dimensional shape combining processing unit creates a three-dimensional structure from the acquired one-dimensional film configurations on the basis of information on the intersection.

摘要翻译： 根据实施例，模拟装置包括二维部分分割处理单元，二维模拟器，一维组合处理单元和三维形状组合处理单元。 二维部分分割处理部将作为模拟对象的三维形状分割为相互交叉的至少一组二维部，并将三维形状定义为二维部。 二维模拟器在通过分割获得的每个二维部分的每个时间步长中进行二维形状模拟，并获得二维形状。 一维组合处理单元从获取的二维形状中提取二维部分的每个交点的胶片配置，并组合胶片配置以获得一维胶片配置。 三维形状组合处理单元根据所获得的一维胶片配置，基于交叉点的信息创建三维结构。

公开(公告)号：US07405088B2

公开(公告)日：2008-07-29

申请号：US10801992

申请日：2004-03-17

申请人： Hiroshi Matsushita ,  Kenichi Kadota ,  Kenji Kawabata ,  Yoshiyuki Shioyama

发明人： Hiroshi Matsushita ,  Kenichi Kadota ,  Kenji Kawabata ,  Yoshiyuki Shioyama

IPC分类号： H01L21/00

CPC分类号： H01L22/20

摘要： A failure analysis method according to the invention includes inputting the positions of failures in multiple wafers of an input device; preparing multiple sections in the multiple wafers; calculating feature amounts, which are represented by at least one numerical value representing a distribution of the failures in the multiple wafers, for each of the multiple sections; and representing by a first numerical value, the degree of similarity between the multiple wafers in terms of the feature amounts. Subsequently, the method includes detecting another wafer, which has the first numerical value greater than a predetermined first threshold, for each of the multiple wafers and forming a similar wafer group of multiple wafers with similar distributions of the failures.

摘要翻译： 根据本发明的故障分析方法包括在输入设备的多个晶片中输入故障的位置; 准备多个晶片的多个部分; 计算特征量，其由表示多个晶片中的故障的分布的至少一个数值表示，用于多个部分中的每一个; 并且通过第一数值表示在特征量方面的多个晶片之间的相似度。 随后，该方法包括对于每个多个晶片检测具有大于预定第一阈值的第一数值的另一个晶片，并且形成具有类似故障分布的多个晶片的相似晶片组。

公开(公告)号：US20060163684A1

公开(公告)日：2006-07-27

申请号：US11387819

申请日：2006-03-24

申请人： Nobuo Nakamura ,  Hisanori Ihara ,  Ikuko Inoue ,  Hidenori Shibata ,  Akiko Nomachi ,  Yoshiyuki Shioyama ,  Hidetoshi Nozaki ,  Masako Hori ,  Akira Makabe ,  Hiroshi Naruse ,  Hideki Inokuma ,  Seigo Abe ,  Hirofumi Yamashita ,  Tetsuya Yamaguchi

发明人： Nobuo Nakamura ,  Hisanori Ihara ,  Ikuko Inoue ,  Hidenori Shibata ,  Akiko Nomachi ,  Yoshiyuki Shioyama ,  Hidetoshi Nozaki ,  Masako Hori ,  Akira Makabe ,  Hiroshi Naruse ,  Hideki Inokuma ,  Seigo Abe ,  Hirofumi Yamashita ,  Tetsuya Yamaguchi

IPC分类号： H01L31/06

CPC分类号： H01L27/14621 ,  H01L27/14601 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14685 ,  H01L31/035236 ,  Y10S257/927

摘要： The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain. The position of an end of the signal accumulating section adjacent to the gate electrode of the MOS transistor extends over the end of the reading gate electrode of the p+ diffusion layer to a position below the gate electrode.

公开(公告)号：US06335220B1

公开(公告)日：2002-01-01

申请号：US09479423

申请日：2000-01-07

申请人： Yoshiyuki Shioyama ,  Hidenori Shibata

发明人： Yoshiyuki Shioyama ,  Hidenori Shibata

IPC分类号： H01L2100

CPC分类号： H01L27/14812

摘要： In a high density solid-state imaging device, of four charge transfer electrodes formed on a semiconductor substrate via a gate insulating film, a first electrode, a fourth electrode, and a part of a second electrode are made of a first conductive film, and a third electrode and the remaining portion of the second electrode are made of a second conductive film. In the second electrode, the first conductive film is joined to the second conductive film. An oxidation film formed by thermally oxidizing the first conductive film isolates the first electrode from the second electrode, the second electrode from the third electrode, and the third electrode from the fourth electrode. The end of the second conductive film is formed so as to locate on the oxidation film on the first conductive film.

摘要翻译： 在高密度固态成像装置中，通过栅极绝缘膜形成在半导体衬底上的四个电荷转移电极，第一电极，第四电极和第二电极的一部分由第一导电膜制成，并且 第三电极，第二电极的剩余部分由第二导电膜制成。 在第二电极中，第一导电膜与第二导电膜接合。 通过热氧化第一导电膜形成的氧化膜将第一电极与第二电极隔离，第二电极与第三电极隔离，第三电极从第四电极隔离。 第二导电膜的端部形成为位于第一导电膜上的氧化膜上。

公开(公告)号：US07043384B2

公开(公告)日：2006-05-09

申请号：US10784819

申请日：2004-02-24

申请人： Hiroshi Matsushita ,  Kenichi Kadota ,  Yoshiyuki Shioyama

发明人： Hiroshi Matsushita ,  Kenichi Kadota ,  Yoshiyuki Shioyama

IPC分类号： G01R31/28 ,  G01R31/00

CPC分类号： G11C29/006 ,  G01R31/01 ,  G11C29/56 ,  G11C2029/0403 ,  G11C2029/5604

摘要： A failure detection system includes a wafer test information input unit which acquires pass/fail maps for wafers for a plurality of types of semiconductor devices, displaying failure chip areas based on results of electrical tests performed on chips; an analogous test information input unit which classifies the electrical tests into analogous electrical tests with regard to analogous failures among the semiconductor devices; a subarea setting unit which assigns subareas common to the types of semiconductor devices on a wafer surface; a characteristic quantity calculation unit which statistically calculates characteristic quantities based on a number of the failure chip areas included in the subareas for each analogous electrical test; and a categorization unit which obtains correlation coefficients between the characteristic quantities corresponding to the subareas, and classifies clustering failure patterns of the failure chip areas into categories by comparing the correlation coefficients with a threshold.

摘要翻译： 故障检测系统包括晶片测试信息输入单元，其获取多种类型的半导体器件的晶片的通过/失败映射，基于对芯片执行的电测试的结果显示故障芯片区域; 类似的测试信息输入单元，其将电测试分类为关于半导体器件中的类似故障的类似电测试; 子区域设定单元，其在晶片表面上分配与所述半导体器件的类型相同的子区域; 特征量计算单元，其基于每个类似电测试在所述子区域中包括的故障码片区域的数量来统计计算特征量; 以及分类单元，其获得与所述子区域相对应的特征量之间的相关系数，并且通过将所述相关系数与阈值进行比较来将所述故障码片区域的聚类故障模式分类。

公开(公告)号：US6028629A

公开(公告)日：2000-02-22

申请号：US829658

申请日：1997-03-31

申请人： Yoshiyuki Shioyama ,  Hidenori Shibata

发明人： Yoshiyuki Shioyama ,  Hidenori Shibata

IPC分类号： H01L21/339 ,  H01L27/148 ,  H01L29/762 ,  H04N5/335 ,  H04N5/341 ,  H04N5/357 ,  H04N5/369 ,  H04N5/372 ,  H04N3/14

CPC分类号： H01L27/14812

摘要： In a high density solid-state imaging device, of four charge transfer electrodes formed on a semiconductor substrate via a gate insulating film, a first electrode, a fourth electrode, and a part of a second electrode are made of a first conductive film, and a third electrode and the remaining portion of the second electrode are made of a second conductive film. In the second electrode, the first conductive film is joined to the second conductive film. An oxidation film formed by thermally oxidizing the first conductive film isolates the first electrode from the second electrode, the second electrode from the third electrode, and the third electrode from the fourth electrode. The end of the second conductive film is formed so as to locate on the oxidation film on the first conductive film.

摘要翻译： 在高密度固态成像装置中，通过栅极绝缘膜形成在半导体衬底上的四个电荷转移电极，第一电极，第四电极和第二电极的一部分由第一导电膜制成，并且 第三电极，第二电极的剩余部分由第二导电膜制成。 在第二电极中，第一导电膜与第二导电膜接合。 通过热氧化第一导电膜形成的氧化膜将第一电极与第二电极隔离，第二电极与第三电极隔离，第三电极从第四电极隔离。 第二导电膜的端部形成为位于第一导电膜上的氧化膜上。

公开(公告)号：US5731601A

公开(公告)日：1998-03-24

申请号：US769380

申请日：1996-12-19

申请人： Yoshiyuki Shioyama ,  Hidenori Shibata

发明人： Yoshiyuki Shioyama ,  Hidenori Shibata

IPC分类号： H01L27/148 ,  H01L29/423 ,  H04N5/335 ,  H04N5/341 ,  H04N5/359 ,  H04N5/369 ,  H04N5/3728 ,  H01L29/768

CPC分类号： H01L27/14812 ,  H01L29/42396

摘要： According to the present invention, there is provided a solid-state imaging device that has a two-layer transfer electrode structure and is based on a four-phase driving all-pixel reading scheme. The transfer gate electrodes for taking the signal charges out of the photodiode PD and transferring them vertically are formed so that the polysilicon electrodes of a first layer and the polysilicon electrodes of a second layer may each have a specific gate length and be in contact with the gate insulating film on a silicon substrate. If four-phase transfer clocks are .phi.1 to .phi.4, the clocks will be applied to the transfer gate electrodes 31, 32 repeatedly in this order for a single pixel (photodiode PD): the second-layer electrode (.phi.2)--the second-layer electrode (.phi.3)--the first-layer electrode (.phi.4)--the first-layer electrode (.phi.1).

摘要翻译： 根据本发明，提供了一种具有双层转移电极结构并且基于四相驱动全像素读取方案的固态成像装置。 用于将信号电荷从光电二极管PD中垂直转移的传输栅电极形成为使得第一层的多晶硅电极和第二层的多晶硅电极可以各自具有特定的栅极长度并且与 栅极绝缘膜在硅衬底上。 如果四相传输时钟为phi 1至phi 4，则时钟将按顺序反复施加到传输栅电极31,32，用于单个像素（光电二极管PD）：第二层电极（phi 2） 第二层电极（phi 3） - 第一层电极（phi 4） - 第一层电极（phi 1）。

公开(公告)号：US08965551B2

公开(公告)日：2015-02-24

申请号：US13050191

申请日：2011-03-17

申请人： Yoshiyuki Shioyama

发明人： Yoshiyuki Shioyama

IPC分类号： G06F19/00 ,  H01L21/66 ,  G01N21/95

CPC分类号： H01L22/12 ,  G01N21/9501 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A defect analyzing method includes acquiring a position and a size of a defect obtained in a defect inspection of a semiconductor device and a waveform of a reflected light in a region which includes the defect, the waveform being obtained in an optical inspection; acquiring process step information which includes a plurality of process steps to manufacture the semiconductor device and a processing content per the process step; performing a process simulation of the semiconductor device based on the position and the size of the defect and the process step information; performing an optical simulation on a result of the process simulation thereby to generate a waveform of a reflected light; calculating a similarity degree between the acquired waveform of the reflected light and the generated waveform of the reflected light; and judging whether or not the calculated similarity degree exceeds a threshold value registered in advance.

摘要翻译： 一种缺陷分析方法，包括获取在半导体器件的缺陷检查中获得的缺陷的位置和尺寸以及包括所述缺陷的区域中的反射光的波形，所述波形是在光学检查中获得的; 获取包括制造半导体器件的多个处理步骤和每个处理步骤的处理内容的处理步骤信息; 基于缺陷的位置和大小以及处理步骤信息执行半导体器件的处理仿真; 对所述过程模拟的结果执行光学仿真，从而产生反射光的波形; 计算所获取的反射光波形与产生的反射光波形之间的相似度; 并且判断计算出的相似度是否超过预先登记的阈值。

公开(公告)号：US5747780A

公开(公告)日：1998-05-05

申请号：US600639

申请日：1996-02-13

申请人： Yoshiyuki Shioyama ,  Masako Hori ,  Koji Kimura

发明人： Yoshiyuki Shioyama ,  Masako Hori ,  Koji Kimura

IPC分类号： B65G54/02 ,  B65G43/00 ,  B65G49/07 ,  H01L21/677 ,  H02K41/02 ,  H05B6/10

CPC分类号： H01L21/67784 ,  Y10S414/137 ,  Y10S414/138 ,  Y10S414/14

摘要： At the front side of a wafer cassette fitted to a wafer feeding unit of a magnetic levitation wafer conveying device, a wafer stopper for preventing the wafer waiting in the wafer cassette from popping out is provided. The wafer supplied from the magnetic levitation conveying device is supplied into the reaction chamber by magnetic force, and is directly held in the reaction chamber by this magnetic force. Since the wafer stopper is positioned between the wafer cassette fitted in the wafer feeding unit and the starting end of the wafer conveying route, the wafer waiting in the wafer cassette next to the wafer to be conveyed is prevented from popping out together with the wafer to be conveyed. Moreover, the wafer conveyed by the magnetic force can be directly held in the reaction chamber in heated state.

摘要翻译： 在安装在磁悬浮晶片输送装置的晶片供给单元的晶片盒的前侧，设置有用于防止晶片盒中的晶片等待突出的晶片止动器。 从磁悬浮输送装置供给的晶片通过磁力供给到反应室，并通过该磁力直接保持在反应室内。 由于晶片止动器位于装配在晶片馈送单元中的晶片盒和晶片输送路径的起始端之间，因此可以防止在晶片盒中等待被输送晶片的晶片与晶片一起弹出 被传达。 此外，通过磁力传送的晶片可以在加热状态下直接保持在反应室中。

公开(公告)号：US07224003B2

公开(公告)日：2007-05-29

申请号：US11387819

申请日：2006-03-24

申请人： Nobuo Nakamura ,  Hisanori Ihara ,  Ikuko Inoue ,  Hidenori Shibata ,  Akiko Nomachi ,  Yoshiyuki Shioyama ,  Hidetoshi Nozaki ,  Masako Hori ,  Akira Makabe ,  Hiroshi Naruse ,  Hideki Inokuma ,  Seigo Abe ,  Hirofumi Yamashita ,  Tetsuya Yamaguchi

发明人： Nobuo Nakamura ,  Hisanori Ihara ,  Ikuko Inoue ,  Hidenori Shibata ,  Akiko Nomachi ,  Yoshiyuki Shioyama ,  Hidetoshi Nozaki ,  Masako Hori ,  Akira Makabe ,  Hiroshi Naruse ,  Hideki Inokuma ,  Seigo Abe ,  Hirofumi Yamashita ,  Tetsuya Yamaguchi

IPC分类号： H01L31/0328

CPC分类号： H01L27/14621 ,  H01L27/14601 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14685 ,  H01L31/035236 ,  Y10S257/927

摘要： The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain. The position of an end of the signal accumulating section adjacent to the gate electrode of the MOS transistor extends over the end of the reading gate electrode of the p+ diffusion layer to a position below the gate electrode.

摘要翻译： 本发明提供一种固态摄像装置，其能够容易地放大信号存储部中的信号电荷，并且不会降低元件的动态范围，处于黑暗状态的热噪声，图像滞后和 所以即使MOS固态摄像装置的像素尺寸减小，读门电压降低，也增加了阱中的浓度。 根据本发明的固态图像拾取装置包括具有用于构成光电转换区域的用于扩散层的表面的p型硅衬底和读取MOS场效应的漏极 形成晶体管。 由p型扩散层的下方形成由n型扩散层形成的信号累积部。 MOS场效应晶体管的栅电极在衬底的表面上形成在扩散层和漏极之间。 与MOS晶体管的栅电极相邻的信号累积部分的端部的位置在p0 +扩散层的读取栅电极的末端延伸到栅电极下方的位置。