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    Simulation apparatus, simulation method and non-transitory computer readable recording medium
    1.
    发明授权
    Simulation apparatus, simulation method and non-transitory computer readable recording medium 有权
    仿真设备，仿真方法和非暂时性计算机可读记录介质

    公开(公告)号：US09183673B2

    公开(公告)日：2015-11-10

    申请号：US13705667

    申请日：2012-12-05

    申请人： Ai Omodaka ,  Yoshiyuki Shioyama ,  Kenji Kawabata

    发明人： Ai Omodaka ,  Yoshiyuki Shioyama ,  Kenji Kawabata

    IPC分类号： G06F9/455 ,  G06F11/22 ,  G06T17/10 ,  G06F17/50

    CPC分类号： G06T17/10 ,  G06F17/5009

    摘要： In accordance with an embodiment, a simulation apparatus includes a two-dimensional section dividing processing unit, a two-dimensional simulator, a one-dimensional combining processing unit, and a three-dimensional shape combining processing unit. The two-dimensional section dividing processing unit divides a three-dimensional shape as a simulation target into at least one set of two-dimensional sections intersecting with each other and defines the three-dimensional shape as the two-dimensional sections. The two-dimensional simulator runs a two-dimensional shape simulation in each time step for each of the two-dimensional sections obtained by the dividing and acquires a two-dimensional shape. The one-dimensional combining processing unit extracts a film configuration for each intersection of the two-dimensional sections from the acquired two-dimensional shape and combines the film configurations to acquire one-dimensional film configurations. The three-dimensional shape combining processing unit creates a three-dimensional structure from the acquired one-dimensional film configurations on the basis of information on the intersection.

    摘要翻译： 根据实施例，模拟装置包括二维部分分割处理单元，二维模拟器，一维组合处理单元和三维形状组合处理单元。 二维部分分割处理部将作为模拟对象的三维形状分割为相互交叉的至少一组二维部，并将三维形状定义为二维部。 二维模拟器在通过分割获得的每个二维部分的每个时间步长中进行二维形状模拟，并获得二维形状。 一维组合处理单元从获取的二维形状中提取二维部分的每个交点的胶片配置，并组合胶片配置以获得一维胶片配置。 三维形状组合处理单元根据所获得的一维胶片配置，基于交叉点的信息创建三维结构。

    Method for analyzing fail bit maps of waters and apparatus therefor
    2.
    发明授权
    Method for analyzing fail bit maps of waters and apparatus therefor 失效
    分析水域及其设备失效位图的方法

    公开(公告)号：US07405088B2

    公开(公告)日：2008-07-29

    申请号：US10801992

    申请日：2004-03-17

    申请人： Hiroshi Matsushita ,  Kenichi Kadota ,  Kenji Kawabata ,  Yoshiyuki Shioyama

    发明人： Hiroshi Matsushita ,  Kenichi Kadota ,  Kenji Kawabata ,  Yoshiyuki Shioyama

    IPC分类号： H01L21/00

    CPC分类号： H01L22/20

    摘要： A failure analysis method according to the invention includes inputting the positions of failures in multiple wafers of an input device; preparing multiple sections in the multiple wafers; calculating feature amounts, which are represented by at least one numerical value representing a distribution of the failures in the multiple wafers, for each of the multiple sections; and representing by a first numerical value, the degree of similarity between the multiple wafers in terms of the feature amounts. Subsequently, the method includes detecting another wafer, which has the first numerical value greater than a predetermined first threshold, for each of the multiple wafers and forming a similar wafer group of multiple wafers with similar distributions of the failures.

    摘要翻译： 根据本发明的故障分析方法包括在输入设备的多个晶片中输入故障的位置; 准备多个晶片的多个部分; 计算特征量，其由表示多个晶片中的故障的分布的至少一个数值表示，用于多个部分中的每一个; 并且通过第一数值表示在特征量方面的多个晶片之间的相似度。 随后，该方法包括对于每个多个晶片检测具有大于预定第一阈值的第一数值的另一个晶片，并且形成具有类似故障分布的多个晶片的相似晶片组。

    Method Of Differentiation From Stem Cells To Hepatocytes
    3.
    发明申请
    Method Of Differentiation From Stem Cells To Hepatocytes 审中-公开
    从干细胞分化为肝细胞的方法

    公开(公告)号：US20120231490A1

    公开(公告)日：2012-09-13

    申请号：US13504149

    申请日：2010-10-22

    申请人： Hiroyuki Mizuguchi ,  Kenji Kawabata ,  Mitsuru Inamura ,  Miho Furue

    发明人： Hiroyuki Mizuguchi ,  Kenji Kawabata ,  Mitsuru Inamura ,  Miho Furue

    IPC分类号： C12N15/861 ,  C12Q1/02 ,  C12N5/10

    CPC分类号： C12N5/067 ,  C12N2500/25 ,  C12N2500/36 ,  C12N2500/44 ,  C12N2500/46 ,  C12N2501/115 ,  C12N2501/119 ,  C12N2501/155 ,  C12N2501/16 ,  C12N2501/60 ,  C12N2501/91 ,  C12N2506/02 ,  C12N2506/45 ,  C12N2510/00

    摘要： Disclosed are: a gene transduction method for use in the induction of the differentiation of stem cells such as ES cells or iPS cells into hepatocytes effectively; stem cells into each of which a gene useful for the induction of the differentiation into hepatocytes is introduced; and hepatocytes produced from stem cells each having the gene introduced therein. A specific gene can be introduced into stem cells such as ES cells or iPS cells using an adenovirus vector. The effective induction of the differentiation into hepatocytes can be achieved by introducing the gene. Specifically, the effective induction of the differentiation of stem cells such as ES cells or iPS cells into hepatocytes can be achieved by introducing at least one gene selected from HEX gene, HNF4A gene, HNF6 gene and SOX17 gene into the stem cells.

    摘要翻译： 公开的是：用于诱导干细胞如ES细胞或iPS细胞分化成肝细胞的基因转导方法; 引入干细胞，其中每一种可用于诱导分化成肝细胞的基因; 和从其中引入基因的干细胞产生的肝细胞。 可以使用腺病毒载体将特定基因导入干细胞如ES细胞或iPS细胞。 可以通过引入基因来实现分化成肝细胞的有效诱导。 具体地说，通过将至少一种选自HEX基因，HNF4A基因，HNF6基因和SOX17基因的基因导入干细胞，可以有效诱导干细胞如ES细胞或iPS细胞分化成肝细胞。

    Power supply apparatus
    9.
    发明授权
    Power supply apparatus 失效
    电源设备

    公开(公告)号：US5705920A

    公开(公告)日：1998-01-06

    申请号：US722510

    申请日：1996-09-27

    申请人： Yoshiteru Watanabe ,  Motohiro Sugino ,  Ryuichi Ikeda ,  Shuzo Matsumoto ,  Kenji Kawabata ,  Takashi Okada

    发明人： Yoshiteru Watanabe ,  Motohiro Sugino ,  Ryuichi Ikeda ,  Shuzo Matsumoto ,  Kenji Kawabata ,  Takashi Okada

    IPC分类号： H05B41/282 ,  G05F1/10 ,  G05F1/40 ,  G05F1/56 ,  H02M3/155

    CPC分类号： G05F1/40

    摘要： A power supply apparatus which stabilizes the output by feeding it back is provided which suppresses variations of the output for abrupt variations of the input. The power supply apparatus comprises output sensing means for sensing output current and output voltage, first output control means for controlling the output with the increment or decrement of the value obtained from said output sensing means, second output control means for controlling the output from an absolute value of the input voltage, and selection means for selecting either said first output control means or said second output control means. The power supply apparatus further comprises means for detecting the variation rate of the input voltage, first monitor means for monitoring the difference between the output value of said output sensing means and the reference value, and second monitor means for monitoring both the difference between the output value of said output sensing means and a reference value, and the input voltage variation rate.

    摘要翻译： 提供通过反馈来稳定输出的电源装置，其抑制输入的突变变化的输出的变化。 电源装置包括用于感测输出电流和输出电压的输出感测装置，用于通过从所述输出感测装置获得的值的增加或减少来控制输出的第一输出控制装置，用于控制来自绝对值的输出的第二输出控制装置 输入电压值，以及用于选择所述第一输出控制装置或所述第二输出控制装置的选择装置。 电源装置还包括用于检测输入电压的变化率的装置，用于监视所述输出检测装置的输出值与参考值之间的差的第一监视装置，以及监视输出 所述输出检测装置的值和参考值以及输入电压变化率。

    Multi-dot flash memory and method of manufacturing the same
    10.
    发明授权
    Multi-dot flash memory and method of manufacturing the same 有权
    多点闪存及其制造方法

    公开(公告)号：US08456908B2

    公开(公告)日：2013-06-04

    申请号：US12563729

    申请日：2009-09-21

    申请人： Takashi Ichikawa ,  Hiroshi Watanabe ,  Kenji Kawabata

    发明人： Takashi Ichikawa ,  Hiroshi Watanabe ,  Kenji Kawabata

    IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  H01L29/788

    CPC分类号： H01L21/28132 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

    摘要： A multi-dot flash memory includes active areas arranged in a first direction, which extend to a second direction crossed to the first direction, the first and second direction being parallel to a surface of a semiconductor substrate, floating gates arranged in the first direction, which are provided above the active areas, a word line provided above the floating gates, which extends to the first direction, and bit lines provided between the floating gates, which extend to the second direction. Each of the floating gates has two side surfaces in the first direction, shapes of the two side surfaces are different from each other, and shapes of the facing surfaces of the floating gates which are adjacent to each other in the first direction are symmetrical.

    摘要翻译： 多点闪速存储器包括沿第一方向布置的有源区域，其延伸到与第一方向交叉的第二方向，第一和第二方向平行于半导体衬底的表面，沿第一方向布置的浮动栅极， 设置在有源区域之上，设置在浮动栅极上方的字线​​，其延伸到第一方向，以及设置在浮动栅极之间的位线，其延伸到第二方向。 每个浮动栅极具有在第一方向上的两个侧表面，两个侧表面的形状彼此不同，并且在第一方向上彼此相邻的浮置栅极的相对表面的形状是对称的。