利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

25 条记录 (耗时 0.031 秒)

    OPTICAL WRITING DEVICE, IMAGE FORMING APPARATUS, AND CONTROL METHOD OF OPTICAL WRITING DEVICE
    1.
    发明申请
    OPTICAL WRITING DEVICE, IMAGE FORMING APPARATUS, AND CONTROL METHOD OF OPTICAL WRITING DEVICE 有权
    光学写字装置，图像形成装置和光写装置的控制方法

    公开(公告)号：US20140049591A1

    公开(公告)日：2014-02-20

    申请号：US13960165

    申请日：2013-08-06

    申请人： Yoshinori SHIRASAKI ,  Tatsuya MIYADERA ,  Masayuki HAYASHI ,  Motohiro KAWANABE ,  Hiroaki IKEDA ,  Tomohiro OHSHIMA ,  Akinori YAMAGUCHI

    发明人： Yoshinori SHIRASAKI ,  Tatsuya MIYADERA ,  Masayuki HAYASHI ,  Motohiro KAWANABE ,  Hiroaki IKEDA ,  Tomohiro OHSHIMA ,  Akinori YAMAGUCHI

    IPC分类号： B41J2/385

    CPC分类号： G03G15/80 ,  G03G15/5004

    摘要： An optical writing device forming an electrical latent image on a photoreceptor includes an optical writing unit configured to apply light to the photoreceptor, a power supply unit configured to supply power to the optical writing unit, a power supply status detector configured to detect a power supply status of the power supplied from the power supply unit to the optical writing unit, and output power supply information or power cutoff information, a power cutoff information retaining unit configured to retain the power cutoff information when the power cutoff information is output from the power supply status detector, and a power sensor configured to sense a power supply status of the power supplied by the power supply unit based on the power cutoff information retained by the power cutoff information retaining unit.

    摘要翻译： 在感光体上形成电潜象的光写入装置包括配置成向感光体施加光的光写入单元，配置为向光写入单元供电的电源单元，电源状态检测器，被配置为检测电源 从电源单元向光学写入单元提供的电力的状态以及输出电源信息或电力切断信息;电力切断信息保持单元，被配置为当从电源输出电力切断信息时保持电力切断信息 状态检测器和被配置为基于由电力切断信息保持单元保持的电力切断信息来感测由电源单元提供的电力的电源状态的功率传感器。

    IMAGE FORMING APPARATUS
    2.
    发明申请
    IMAGE FORMING APPARATUS 有权
    图像形成装置

    公开(公告)号：US20130343775A1

    公开(公告)日：2013-12-26

    申请号：US13917874

    申请日：2013-06-14

    申请人： Akinori YAMAGUCHI ,  Hiroaki IKEDA ,  Tomohiro OHSHIMA ,  Masayuki HAYASHI ,  Tatsuya MIYADERA ,  Motohiro KAWANABE ,  Yoshinori SHIRASAKI

    发明人： Akinori YAMAGUCHI ,  Hiroaki IKEDA ,  Tomohiro OHSHIMA ,  Masayuki HAYASHI ,  Tatsuya MIYADERA ,  Motohiro KAWANABE ,  Yoshinori SHIRASAKI

    IPC分类号： G03G15/00 ,  G03G15/01

    CPC分类号： G03G15/01 ,  G03G15/5008 ,  G03G15/505 ,  G03G15/5054 ,  G03G2215/00569 ,  G03G2215/00599 ,  G03G2215/00949

    摘要： An image forming apparatus comprises: an image forming unit configured to form an image quality adjustment pattern image on an image carrier to be driven at a predetermined speed; a detector configured to detect the image quality adjustment pattern image; an image quality adjustment controller configured to control image quality adjustment processing in accordance with a detection result by the detector; a speed change unit configured to change an image formation speed indicating a speed at which an image is formed, and an interval change unit configured to change an interval at which the detector acquires a detection result in accordance with a change amount between the image formation speed before changed by the speed change unit and the image formation speed after changed.

    摘要翻译： 图像形成装置包括：图像形成单元，被配置为在要以预定速度驱动的图像载体上形成图像质量调整图案图像; 检测器，被配置为检测图像质量调整图案图像; 图像质量调整控制器，被配置为根据检测器的检测结果来控制图像质量调整处理; 速度改变单元，被配置为改变指示形成图像的速度的图像形成速度;以及间隔改变单元，被配置为根据图像形成速度之间的变化量来改变检测器获取检测结果的间隔 之前由变速单元改变后的图像形成速度改变。

    IMAGE FORMING APPARATUS AND METHOD FOR CONTROLLING THE SAME
    3.
    发明申请
    IMAGE FORMING APPARATUS AND METHOD FOR CONTROLLING THE SAME 有权
    图像形成装置及其控制方法

    公开(公告)号：US20130242318A1

    公开(公告)日：2013-09-19

    申请号：US13782248

    申请日：2013-03-01

    申请人： Akinori YAMAGUCHI ,  Masayuki HAYASHI ,  Hiroaki IKEDA ,  Kunihiro KOMAI ,  Tatsuya MIYADERA ,  Takeshi SHIKAMA ,  Takuhei YOKOYAMA ,  Yoshinori SHIRASAKI ,  Motohiro KAWANABE

    发明人： Akinori YAMAGUCHI ,  Masayuki HAYASHI ,  Hiroaki IKEDA ,  Kunihiro KOMAI ,  Tatsuya MIYADERA ,  Takeshi SHIKAMA ,  Takuhei YOKOYAMA ,  Yoshinori SHIRASAKI ,  Motohiro KAWANABE

    IPC分类号： G06K15/02

    CPC分类号： G06K15/1878 ,  G03G15/5058 ,  G03G2215/0141

    摘要： In the invention, an inclination amount of sensors is reflected in positional deviation correction patterns, and for correcting formation positions of images of various colors, the positional deviation correction patterns are formed on a conveying belt. The positional deviation correction patterns are detected by the sensors. A control unit calculates positional deviation correction amounts based on detection results of the positional deviation correction patterns. Based on the calculated positional deviation correction amounts, the control unit performs calculation for correcting the positional deviation correction patterns, and cancels the inclination amount reflected in the calculation results to obtain final positional deviation correction amounts. Skew correction is performed based on the final positional deviation correction amounts, and thus, the positional deviations are corrected.

    摘要翻译： 在本发明中，传感器的倾斜量反映在位置偏差校正图案中，并且为了校正各种图像的形成位置，在输送带上形成位置偏差校正图案。 位置偏差校正图案由传感器检测。 控制单元基于位置偏差校正图案的检测结果来计算位置偏差校正量。 基于所计算的位置偏差校正量，控制单元进行用于校正位置偏差校正图案的计算，并且取消反映在计算结果中的倾斜量，以获得最终位置偏差校正量。 基于最终位置偏差校正量执行偏斜校正，因此校正位置偏差。

    IMAGE FORMING APPARATUS, MISREGISTRATION CORRECTION CONTROL METHOD AND COMPUTER-READABLE INFORMATION RECORDING MEDIUM
    7.
    发明申请
    IMAGE FORMING APPARATUS, MISREGISTRATION CORRECTION CONTROL METHOD AND COMPUTER-READABLE INFORMATION RECORDING MEDIUM 失效
    图像形成装置，误差校正控制方法和计算机可读信息记录介质

    公开(公告)号：US20090213399A1

    公开(公告)日：2009-08-27

    申请号：US12390554

    申请日：2009-02-23

    申请人： Hiroaki IKEDA

    发明人： Hiroaki IKEDA

    IPC分类号： G06F15/00

    CPC分类号： G03G15/5058 ,  G03G15/0194 ,  G03G2215/00059 ,  G03G2215/00063 ,  G03G2215/0161

    摘要： A pattern image of either a registration correction pattern including a plurality of position detecting marks or a misregistration correction performing determination pattern having a plurality of position detecting marks, the number of which marks is smaller than that of the registration correction pattern image is formed. A misregistration amount is calculated based on an image formed position detected with the use of the pattern image. It is determined whether the registration correction is to be carried out, based on the misregistration amount with the use of an image formed position of the correction performing determination pattern. When it is determined to carry out the misregistration correction, the misregistration correction is carried out based on the misregistration amount with the use of image formed positions of the misregistration correction pattern.

    摘要翻译： 形成包括多个位置检测标记的注册校正图案或者具有多个位置检测标记的不对准校正执行确定模式的图案图像，其数量比注册校正图案图像的数量小。 基于通过使用图案图像检测到的图像形成位置来计算不对准量。 基于通过使用校正执行确定模式的图像形成位置的不对准量来确定是否要执行登记校正。 当确定执行不对准校正时，通过使用不对准校正图案的图像形成位置，基于不对准量来执行重新排列校正。

    STACKED TYPE SEMICONDUCTOR MEMORY DEVICE AND CHIP SELECTION CIRCUIT
    8.
    发明申请
    STACKED TYPE SEMICONDUCTOR MEMORY DEVICE AND CHIP SELECTION CIRCUIT 失效
    堆叠型半导体存储器件和芯片选择电路

    公开(公告)号：US20120122251A1

    公开(公告)日：2012-05-17

    申请号：US13293897

    申请日：2011-11-10

    申请人： Junji YAMADA ,  Hiroaki IKEDA ,  Kayoko SHIBATA ,  Yoshihiko INOUE ,  Hitoshi MIWA ,  Tatsuya IJIMA

    发明人： Junji YAMADA ,  Hiroaki IKEDA ,  Kayoko SHIBATA ,  Yoshihiko INOUE ,  Hitoshi MIWA ,  Tatsuya IJIMA

    IPC分类号： H01L21/66

    CPC分类号： H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  G11C2029/4402 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/01021 ,  H01L2924/15311

    摘要： A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.

    摘要翻译： 通过分配彼此不同的多个芯片标识号，具有堆叠多个半导体芯片的结构和可以选择期望的半导体芯片的堆叠型半导体存储器件被分别分配给多个半导体芯片，包括： 多个操作电路，其以所述多个半导体芯片的堆叠顺序级联连接，并通过执行预定的操作输出所述多个不同的识别号码; 以及多个比较电路，通过比较它们来检测每个半导体芯片共同连接的每个识别号码和芯片选择地址是否相等。

    MEMORY MODULE AND MEMORY SYSTEM
    9.
    发明申请
    MEMORY MODULE AND MEMORY SYSTEM 有权
    存储器模块和存储器系统

    公开(公告)号：US20110141789A1

    公开(公告)日：2011-06-16

    申请号：US13033424

    申请日：2011-02-23

    申请人： Yoshinori MATSUI ,  Toshio SUGANO ,  Hiroaki IKEDA

    发明人： Yoshinori MATSUI ,  Toshio SUGANO ,  Hiroaki IKEDA

    IPC分类号： G11C5/02

    CPC分类号： G11C11/408 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1051 ,  G11C7/1063 ,  G11C8/12 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/0401

    摘要： In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

    摘要翻译： 在包括以预定数据宽度和传送速率发送/接收系统数据信号的多个DRAM芯片的存储器模块中，并且发送/接收具有较大数据宽度和较低传输速率的内部数据信号与 系统数据信号，系统数据信号的传输速率受到限制。 构成存储器模块的DRAM的电流消耗大，阻碍速度增加。 对于该存储器模块，多个DRAM芯片堆叠在IO芯片上。 每个DRAM芯片通过贯通电极连接到IO芯片，并且包括用于通过IO芯片相互转换每个DRAM芯片中的系统数据信号和内部数据信号的结构。 因此，可以缩短DRAM芯片之间的布线，并且可以仅在IO芯片上设置具有大电流消耗的DLL。