公开(公告)号：US08541768B2

公开(公告)日：2013-09-24

申请号：US13118402

申请日：2011-05-28

申请人： Akio Shima ,  Yoshitska Sasago ,  Toshiyuki Mine ,  Masaharu Kinoshita

发明人： Akio Shima ,  Yoshitska Sasago ,  Toshiyuki Mine ,  Masaharu Kinoshita

IPC分类号： H01L29/02

CPC分类号： H01L27/2454 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A technique used for a semiconductor device formed by stacking multiple structural bodies each having a semiconductor device, for preventing generation of thermal load on a structural body at a lower layer which is caused by a laser used in a step of forming a structural body at an upper layer. In a phase-change memory including multiple stacked memory matrices, a metal film is disposed between a memory matrix at a lower layer and a memory matrix at an upper layer formed over the memory matrix at the lower layer, in which the laser used for forming the memory matrix is reflected at the metal film and prevented from transmitting the metal film, thereby preventing the phase-change material layer, etc. in the memory matrix at the lower layer from being directly heated excessively by the laser.

摘要翻译： 一种用于半导体器件的技术，该半导体器件通过堆叠多个具有半导体器件的结构体而形成，用于防止由在用于形成结构体的步骤中使用的激光器引起的下层的结构体上的热负荷的产生 上层。 在包括多个堆叠的存储器矩阵的相变存储器中，金属膜设置在下层的存储矩阵和在下层的存储矩阵上形成的上层的存储矩阵之间，其中用于形成的激光 存储矩阵在金属膜处被反射并且防止金属膜透射，从而防止下层的存储矩阵中的相变材料层等被激光过度直接加热。

公开(公告)号：US08427865B2

公开(公告)日：2013-04-23

申请号：US13440225

申请日：2012-04-05

申请人： Akio Shima ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

发明人： Akio Shima ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

IPC分类号： G11C11/00 ,  H01L29/80

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1683

摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

摘要翻译： 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以构成三维存储器 单元格阵列。 存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。 通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

公开(公告)号：US08169819B2

公开(公告)日：2012-05-01

申请号：US12688886

申请日：2010-01-17

申请人： Akio Shima ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

发明人： Akio Shima ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

IPC分类号： G11C11/00 ,  H01L29/80

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1683

摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

摘要翻译： 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以配置三维存储器 单元格阵列。 存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。 通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

公开(公告)号：US20090085042A1

公开(公告)日：2009-04-02

申请号：US12219837

申请日：2008-07-29

申请人： Toshiyuki Mine ,  Mitsuharu Tai ,  Akio Shima

发明人： Toshiyuki Mine ,  Mitsuharu Tai ,  Akio Shima

IPC分类号： H01L21/20 ,  H01L29/04

CPC分类号： H01L21/268 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/02686 ,  H01L27/1285 ,  H01L29/78642

摘要： A display device having a thin film semiconductor device including a semiconductor thin film having first and second semiconductor regions formed each into a predetermined shape above an insulative substrate, a conductor fabricated into a predetermined shape to the semiconductor thin film and a dielectric film put between the semiconductor thin film and the conductor, in which the semiconductor thin film is a polycrystal thin film with the crystallization ratio thereof exceeding 90% and the difference of unevenness on the surface of the semiconductor thin film does not exceed 10 nm.

摘要翻译： 一种具有薄膜半导体器件的显示装置，该薄膜半导体器件包括半导体薄膜，该半导体薄膜具有在绝缘性基板的上方形成为规定形状的第一半导体区域和第二半导体区域，对该半导体薄膜形成为规定形状的导体， 半导体薄膜和导体，其中半导体薄膜是结晶比率超过90％的多晶薄膜，并且半导体薄膜的表面上的不均匀度不超过10nm。

公开(公告)号：US20130228739A1

公开(公告)日：2013-09-05

申请号：US13884263

申请日：2010-12-06

申请人： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Mitsuharu Tai ,  Akio Shima ,  Kenzo Kurotsuchi ,  Takashi Kobayashi

发明人： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Mitsuharu Tai ,  Akio Shima ,  Kenzo Kurotsuchi ,  Takashi Kobayashi

IPC分类号： H01L45/00

CPC分类号： H01L45/1608 ,  G11C13/0004 ,  G11C2213/75 ,  H01L27/0688 ,  H01L27/1021 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/7926 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

摘要： When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.

摘要翻译： 当在叠层薄膜上除去形成在绝缘膜和栅电极交替层叠在一起的叠层膜的侧壁上的薄沟道半导体层时，包括沟道半导体层的垂直晶体管与栅电极之间的接触电阻， 并且防止形成在层叠膜上的位线上升。 作为其手段，电连接到沟道半导体层的导电层设置在堆叠膜的正上方。

公开(公告)号：US07906834B2

公开(公告)日：2011-03-15

申请号：US12219837

申请日：2008-07-29

申请人： Toshiyuki Mine ,  Mitsuharu Tai ,  Akio Shima

发明人： Toshiyuki Mine ,  Mitsuharu Tai ,  Akio Shima

IPC分类号： H01L23/552

CPC分类号： H01L21/268 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/02686 ,  H01L27/1285 ,  H01L29/78642

摘要： A display device having a thin film semiconductor device including a semiconductor thin film having first and second semiconductor regions formed each into a predetermined shape above an insulative substrate, a conductor fabricated into a predetermined shape to the semiconductor thin film and a dielectric film put between the semiconductor thin film and the conductor, in which the semiconductor thin film is a polycrystal thin film with the crystallization ratio thereof exceeding 90% and the difference of unevenness on the surface of the semiconductor thin film does not exceed 10 nm.

摘要翻译： 一种具有薄膜半导体器件的显示装置，该薄膜半导体器件包括半导体薄膜，该半导体薄膜具有在绝缘性基板的上方形成为规定形状的第一半导体区域和第二半导体区域，对该半导体薄膜形成为规定形状的导体， 半导体薄膜和导体，其中半导体薄膜是结晶比率超过90％的多晶薄膜，并且半导体薄膜的表面上的不均匀度不超过10nm。

公开(公告)号：US08866123B2

公开(公告)日：2014-10-21

申请号：US13884331

申请日：2010-11-22

申请人： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Takahiro Morikawa ,  Akio Shima ,  Takashi Kobayashi

发明人： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Takahiro Morikawa ,  Akio Shima ,  Takashi Kobayashi

IPC分类号： H01L47/00 ,  H01L45/00 ,  H01L29/792 ,  H01L27/24 ,  H01L29/66 ,  H01L27/115

CPC分类号： H01L27/2436 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/66833 ,  H01L29/7926 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1683

摘要： A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.

摘要翻译： 垂直链式存储器包括具有第一选择晶体管的两层选择晶体管，它们是以矩阵形式排列的垂直晶体管，第二选择晶体管是形成在各个第一选择晶体管上的垂直晶体管，以及多个存储单元串联连接 双层选择晶体管。 利用这种配置，防止相邻的选择晶体管被相应的共享栅极选择，可以独立地选择多个两层选择晶体管，并且防止非易失性存储装置的存储容量减小。

公开(公告)号：US08790948B2

公开(公告)日：2014-07-29

申请号：US13303227

申请日：2011-11-23

申请人： Keiji Watanabe ,  Toshiyuki Mine ,  Akio Shima ,  Tomoko Sekiguchi ,  Ryuta Tsuchiya

发明人： Keiji Watanabe ,  Toshiyuki Mine ,  Akio Shima ,  Tomoko Sekiguchi ,  Ryuta Tsuchiya

IPC分类号： H01L21/00

CPC分类号： H01L31/02168 ,  B82Y20/00 ,  H01L31/0352 ,  H01L31/035236 ,  H01L31/055 ,  H01L31/075 ,  H01L31/1872 ,  Y02E10/52 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

摘要： In the existent method for manufacturing a solar cell, manufacture of a solar cell having a quantum well having a crystalline well layer and capable of controlling the thickness of the well layer was difficult. A quantum well having an amorphous well layer, comprising a barrier layer and an amorphous well layer is formed and then the quantum well having the amorphous well layer is annealed thereby crystallizing the amorphous well layer to form a quantum well having a crystalline well layer. By applying energy density applied to the amorphous well layer at an energy density of 1.26 J/mm2 or more and 28.8 J/mm2 or less, the crystalline well layer can be formed and the lamination structure of the quantum well can be maintained simultaneously.

摘要翻译： 在制造太阳能电池的现有方法中，难以制造具有具有结晶阱层并能够控制阱层的厚度的量子阱的太阳能电池。 形成具有非晶阱层的量子阱，其包含阻挡层和非晶阱层，然后对具有非晶阱层的量子阱退火，从而使非晶阱层结晶，形成具有结晶阱层的量子阱。 通过以1.26J / mm 2以上且28.8J / mm 2以下的能量密度施加到非晶质阱层的能量密度，可以形成结晶阱层，同时可以维持量子阱的层叠结构。

公开(公告)号：US07838379B2

公开(公告)日：2010-11-23

申请号：US12362277

申请日：2009-01-29

申请人： Masaharu Kinoshita ,  Motoyasu Terao ,  Hideyuki Matsuoka ,  Yoshitaka Sasago ,  Yoshinobu Kimura ,  Akio Shima ,  Mitsuharu Tai ,  Norikatsu Takaura

发明人： Masaharu Kinoshita ,  Motoyasu Terao ,  Hideyuki Matsuoka ,  Yoshitaka Sasago ,  Yoshinobu Kimura ,  Akio Shima ,  Mitsuharu Tai ,  Norikatsu Takaura

IPC分类号： H01L21/20

CPC分类号： H01L21/8221 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1285 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： In a phase change memory, electric property of a diode used as a selection device is extremely important. However, since crystal grain boundaries are present in the film of a diode using polysilicon, it involves a problem that the off leak property varies greatly making it difficult to prevent erroneous reading. For overcoming the problem, the present invention provides a method of controlling the temperature profile of an amorphous silicon in the laser annealing for crystallizing and activating the amorphous silicon thereby controlling the crystal grain boundaries. According to the invention, variation in the electric property of the diode can be decreased and the yield of the phase-change memory can be improved.

摘要翻译： 在相变存储器中，用作选择装置的二极管的电特性非常重要。 然而，由于在使用多晶硅的二极管的膜中存在晶界，所以存在泄漏特性变化很大的问题，难以防止误读。 为了解决这个问题，本发明提供了一种在激光退火中控制非晶硅的温度分布的方法，用于结晶和激活非晶硅，从而控制晶界。 根据本发明，可以降低二极管的电性能的变化，并且可以提高相变存储器的产量。

公开(公告)号：US20090189137A1

公开(公告)日：2009-07-30

申请号：US12362277

申请日：2009-01-29

申请人： Masaharu Kinoshita ,  Motoyasu Terao ,  Hideyuki Matsuoka ,  Yoshitaka Sasago ,  Yoshinobu Kimura ,  Akio Shima ,  Mitsuharu Tai ,  Norikatsu Takaura

发明人： Masaharu Kinoshita ,  Motoyasu Terao ,  Hideyuki Matsuoka ,  Yoshitaka Sasago ,  Yoshinobu Kimura ,  Akio Shima ,  Mitsuharu Tai ,  Norikatsu Takaura

IPC分类号： H01L47/00

CPC分类号： H01L21/8221 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1285 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： In a phase change memory, electric property of a diode used as a selection device is extremely important. However, since crystal grain boundaries are present in the film of a diode using polysilicon, it involves a problem that the off leak property varies greatly making it difficult to prevent erroneous reading. For overcoming the problem, the present invention provides a method of controlling the temperature profile of an amorphous silicon in the laser annealing for crystallizing and activating the amorphous silicon thereby controlling the crystal grain boundaries. According to the invention, variation in the electric property of the diode can be decreased and the yield of the phase-change memory can be improved.

摘要翻译： 在相变存储器中，用作选择装置的二极管的电特性非常重要。 然而，由于在使用多晶硅的二极管的膜中存在晶界，所以存在泄漏特性变化很大的问题，难以防止误读。 为了解决这个问题，本发明提供了一种在激光退火中控制非晶硅的温度分布的方法，用于结晶和激活非晶硅，从而控制晶界。 根据本发明，可以降低二极管的电性能的变化，并且可以提高相变存储器的产量。