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43 条记录 (耗时 0.028 秒)

    Resin encapsulation type semiconductor device
    7.
    发明授权
    Resin encapsulation type semiconductor device 失效
    树脂封装型半导体器件

    公开(公告)号：US5346743A

    公开(公告)日：1994-09-13

    申请号：US28696

    申请日：1993-03-08

    申请人： Ken Uchida ,  Michiya Higashi ,  Shinetsu Fujieda

    发明人： Ken Uchida ,  Michiya Higashi ,  Shinetsu Fujieda

    IPC分类号： C08G59/32 ,  C08G59/68 ,  C08L63/00 ,  H01B3/40 ,  H01L23/29

    CPC分类号： H01L23/293 ,  C08G59/3218 ,  C08G59/686 ,  C08L63/00 ,  H01B3/40 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2924/1433 ,  H01L2924/181 ,  Y10T428/239

    摘要： According to a first embodiment of the present invention, there is provided a resin encapsulation type semiconductor device, comprising a semiconductor element and an epoxy resin composition used as an encapsulating resin, the composition containing as essential components:(a) an epoxy resin represented by formula (I) given below: ##STR1## where R.sup.1, R.sup.2, R.sup.3, and R.sup.4 are hydrogen or an alkyl group respectively, and n.gtoreq.0,(b) a phenolic resin curing agent,(c) an imidazole compound, and(d) triphenyl phosphate.In the first embodiment of the present invention, a heat resistance skeletal structure is formed by the epoxy resin (a) and the phenolic resin curing agent (b) in the epoxy resin composition after cured, leading to an improved resistance to heat and to an improved package crack resistance. Further, the combination of the imidazole compound (c) used as a curing catalyst and triphenyl phosphate (d) permits ensuring a high reliability in terms of the humidity resistance and also permits improving the resistance to the external contamination.

    摘要翻译： 根据本发明的第一实施例，提供一种树脂封装型半导体器件，其包含半导体元件和用作封装树脂的环氧树脂组合物，该组合物含有作为必要成分的组合物：（a）由 式（I）：其中R1，R2，R3和R4分别是氢或烷基，n≥0，（b）酚醛树脂固化剂，（c） 咪唑化合物和（d）磷酸三苯酯。 在本发明的第一实施方案中，环氧树脂组合物中的环氧树脂（a）和酚醛树脂固化剂（b）在固化后形成耐热骨架结构，导致耐热性提高 提高包装抗裂性。 此外，用作固化催化剂的咪唑化合物（c）和磷酸三苯酯（d）的组合可以确保在耐湿性方面的高可靠性，并且还可以改善对外部污染的抵抗力。

    Non-volatile semiconductor storage device and method for manufacturing the same
    8.
    发明授权
    Non-volatile semiconductor storage device and method for manufacturing the same 失效
    非易失性半导体存储装置及其制造方法

    公开(公告)号：US07737486B2

    公开(公告)日：2010-06-15

    申请号：US11859142

    申请日：2007-09-21

    申请人： Masumi Saitoh ,  Ken Uchida

    发明人： Masumi Saitoh ,  Ken Uchida

    IPC分类号： H01L29/788

    CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/165 ,  H01L29/7881

    摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.

    摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 源极区域和漏极区域，形成在半导体衬底中以便彼此分离; 在所述半导体衬底上形成在所述源极区域和所述漏极区域之间的第一绝缘膜; 形成在所述第一绝缘膜上并具有延伸应变的半导体导电材料层的浮动电极; 形成在浮置电极上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制电极。 浮动电极的延伸应变随着位置从第二绝缘膜向第一绝缘膜前进而逐渐变小，浮动电极在浮动电极和第二绝缘膜之间的界面具有0.01％以上的延伸应变， 并且在浮动电极和第一绝缘膜之间的界面处具有小于0.01％的延伸应变。

    Semiconductor device with negative differential resistance characteristics
    9.
    发明授权
    Semiconductor device with negative differential resistance characteristics 失效
    具有负差分电阻特性的半导体器件

    公开(公告)号：US06690030B2

    公开(公告)日：2004-02-10

    申请号：US09798923

    申请日：2001-03-06

    申请人： Junji Koga ,  Ken Uchida ,  Ryuji Ohba ,  Akira Toriumi

    发明人： Junji Koga ,  Ken Uchida ,  Ryuji Ohba ,  Akira Toriumi

    IPC分类号： H01L2940

    CPC分类号： H01L27/1104 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/511 ,  H01L29/7881

    摘要： A gate oxide film formed on the surface of a silicon substrate is partly reduced in thickness or “thinned” at its specified part overlying a source region. In a gate region, a multilayer structure is formed which includes a first polycrystalline silicon or “polysilicon” film of a p-type conductivity, a tunnel oxide film, and a second p-type polysilicon film in this order of lamination. The source region and the first polysilicon film make up a high-concentration impurity-doped pn junction with a thin silicon oxide film laid therebetween, providing a tunnel diode also known as Esaki diode. The diode is used for a negative differential resistance. Further, a portion between the first and second polysilicon films is a non-linear tunnel resistor, which serves as a load. The negative differential resistance and the load are serially connected together between a low-voltage power supply (ground potential) Vss and a high-voltage power supply Vdd, thus enabling forming a transistor with a built-in bistable circuit. Potential information of the first polysilicon film for use as a data storage node is read with a transistor amplification applied thereto. Thus, data read is performed at high speeds. Simultaneously, a current flowing between the power supplies is suppressed to a lower level, thereby minimizing power consumption in wait modes.

    摘要翻译： 形成在硅衬底表面上的栅极氧化膜的厚度部分地减小或者在其源区域上的指定部分“薄化”。 在栅极区域中，以层叠的顺序形成包括p型导电体的第一多晶硅或“多晶硅”膜，隧道氧化物膜和第二p型多晶硅膜的多层结构。 源极区域和第一多晶硅膜构成了高浓度杂质掺杂的pn结，其间铺设有薄的氧化硅膜，提供了也称为Esaki二极管的隧道二极管。 二极管用于负差分电阻。 此外，第一和第二多晶硅膜之间的部分是用作负载的非线性隧道电阻器。 负的差分电阻和负载在低压电源（接地电位）Vss和高压电源Vdd之间串联连接在一起，从而能够形成具有内置双稳态电路的晶体管。 读取用作数据存储节点的第一多晶硅膜的电位信息，并施加晶体管放大。 因此，高速执行数据读取。 同时，在电源之间流动的电流被抑制到较低的电平，从而使等待模式中的功耗最小化。