PFET Nonvolatile Memory
    1.
    发明申请
    PFET Nonvolatile Memory 有权
    PFET非易失性存储器

    公开(公告)号:US20120099380A1

    公开(公告)日:2012-04-26

    申请号:US13342834

    申请日:2012-01-03

    IPC分类号: G11C16/10 G11C16/04

    摘要: A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.

    摘要翻译: 使用其源极连接到电源(Vdd)的浮栅pFET读出晶体管构造非易失性存储单元,其漏极提供电流,其可以被感测以确定单元的状态。 pFET读出晶体管的栅极提供电荷存储,可用于表示诸如二进制位之类的信息。 耦合在第一电压源和浮动栅极之间的控制电容器和在第二电压源和浮置栅极之间的隧道电容器被制造成使得控制电容器具有比隧道电容器多得多的电容。 施加到第一电压源和第二电压源的电压的操作控制电容器结构和pFET电介质两端的电场,从而Fowler-Nordheim在浮栅上和从浮栅上隧穿隧道,控制浮栅上的电荷和信息 存储在其上。

    pFET nonvolatile memory
    3.
    发明授权
    pFET nonvolatile memory 有权
    pFET非易失性存储器

    公开(公告)号:US08111558B2

    公开(公告)日:2012-02-07

    申请号:US11865777

    申请日:2007-10-02

    IPC分类号: G11C11/34

    摘要: A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.

    摘要翻译: 使用其源极连接到电源(Vdd)的浮栅pFET读出晶体管构造非易失性存储单元,其漏极提供电流,其可以被感测以确定单元的状态。 pFET读出晶体管的栅极提供电荷存储,可用于表示诸如二进制位之类的信息。 耦合在第一电压源和浮动栅极之间的控制电容器和在第二电压源和浮置栅极之间的隧道电容器被制造成使得控制电容器具有比隧道电容器多得多的电容。 施加到第一电压源和第二电压源的电压的操作控制电容器结构和pFET电介质两端的电场,从而Fowler-Nordheim在浮栅上和从浮栅上隧穿隧道,控制浮栅上的电荷和信息 存储在其上。

    PFET nonvolatile memory
    4.
    发明授权
    PFET nonvolatile memory 有权
    PFET非易失性存储器

    公开(公告)号:US08416630B2

    公开(公告)日:2013-04-09

    申请号:US13342834

    申请日:2012-01-03

    IPC分类号: G11C11/34

    摘要: A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.

    摘要翻译: 使用其源极连接到电源(Vdd)的浮栅pFET读出晶体管构造非易失性存储单元,其漏极提供电流,其可以被感测以确定单元的状态。 pFET读出晶体管的栅极提供电荷存储,可用于表示诸如二进制位之类的信息。 耦合在第一电压源和浮动栅极之间的控制电容器和在第二电压源和浮置栅极之间的隧道电容器被制造成使得控制电容器具有比隧道电容器多得多的电容。 施加到第一电压源和第二电压源的电压的操作控制电容器结构和pFET电介质两端的电场,从而Fowler-Nordheim隧穿电子在浮栅上和离开浮栅,控制浮栅上的电荷和信息 存储在其上。

    RFID tags circuits and methods for sensing own power to predetermine feasibility of requested action
    5.
    发明授权
    RFID tags circuits and methods for sensing own power to predetermine feasibility of requested action 有权
    RFID标签电路和用于感测自身电力的方法,以预先确定所请求动作的可行性

    公开(公告)号:US07733227B1

    公开(公告)日:2010-06-08

    申请号:US11624197

    申请日:2007-01-17

    IPC分类号: G08B13/14

    摘要: Feasibility of a requested action by a reader is predetermined in an RFID tag based on an available tag power level. A pretest that is designed to consume artificially high levels of power is performed and the power level monitored to determine if a preset condition is met. The pretest may include activation of selected components such as a memory and associated support circuitry. If the preset condition is not met, the requested action is aborted and an error message transmitted to the reader.

    摘要翻译: 基于可用的标签功率电平,RFID标签中预先确定读取器所请求的动作的可行性。 执行被设计为消耗人为高电平的预测试,并且监视功率电平以确定是否满足预设条件。 预测试可以包括激活所选择的组件,例如存储器和相关联的支持电路。 如果不满足预设条件,请求的操作将中止,并将错误消息传送给读卡器。

    pFET nonvolatile memory
    6.
    发明授权
    pFET nonvolatile memory 有权
    pFET非易失性存储器

    公开(公告)号:US07221596B2

    公开(公告)日:2007-05-22

    申请号:US10839985

    申请日:2004-05-05

    IPC分类号: G11C16/06

    摘要: A nonvolatile memory cell is constructed using a floating-gate (FG) pFET Readout Transistor (RT) having its source tied to a power source (Vdd) and its drain providing a current which can be sensed to determine a cell state. The gate of the RT provides for charge/information storage. A control capacitor structure (CCS) having terminals coupled to a first voltage source and the FG and a tunneling capacitor structure (TCS) having terminals coupled to a second voltage source and the FG are utilized in each embodiment. The CCS has much more capacitance than the TCS. Manipulation of the voltages applied to the first voltage source and second voltage source (and Vdd) controls an electric field across the CCS and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons onto and off of the FG, thus controlling the charge on the FG and the information stored thereon.

    摘要翻译: 使用其源极连接到电源(Vdd)的浮栅(FG)pFET读出晶体管(RT)构成非易失性存储单元,其漏极提供可被感测以确定单元状态的电流。 RT的门提供充电/信息存储。 具有耦合到第一电压源的端子和具有耦合到第二电压源和FG的端子的隧道电容器结构(TCS)的控制电容器结构(CCS)在每个实施例中被使用。 CCS具有比TCS多得多的电容。 对施加到第一电压源和第二电压源(和Vdd)的电压的操纵控制跨越CCS和pFET电介质的电场,并且因此Fowler-Nordheim隧道电子进入FG和FG,从而控制FG上的电荷 以及存储在其上的信息。

    PFET nonvolatile memory
    8.
    发明授权
    PFET nonvolatile memory 有权
    PFET非易失性存储器

    公开(公告)号:US07894261B1

    公开(公告)日:2011-02-22

    申请号:US12239696

    申请日:2008-09-26

    申请人: Alberto Pesavento

    发明人: Alberto Pesavento

    IPC分类号: G11C11/34

    CPC分类号: G11C16/0441 H01L27/11558

    摘要: A non-volatile memory integrated circuit includes multiple memory cells, each memory cell including a first MOS transistor, a first control capacitor, and a first floating gate coupled to the first MOS transistor and the first control capacitor. A first read/write control signal is provided having at least a first state and a second state and coupled the first MOS transistor. When the control signal is in the first state, the memory cell is configured for readout, and when the control signal is in the second state, the memory cell is configured for writing. Both single-ended and differential memory cells are described. Arrays of such nonvolatile memory cells are also described.

    摘要翻译: 非易失性存储器集成电路包括多个存储器单元,每个存储单元包括第一MOS晶体管,第一控制电容器和耦合到第一MOS晶体管和第一控制电容器的第一浮置栅极。 提供具有至少第一状态和第二状态并且耦合第一MOS晶体管的第一读/写控制信号。 当控制信号处于第一状态时,存储单元被配置为用于读出,并且当控制信号处于第二状态时,存储单元被配置为写入。 描述单端和差分存储器单元。 还描述了这种非易失性存储单元的阵列。

    PFET nonvolatile memory
    10.
    发明申请
    PFET nonvolatile memory 有权
    PFET非易失性存储器

    公开(公告)号:US20050063235A1

    公开(公告)日:2005-03-24

    申请号:US10839985

    申请日:2004-05-05

    摘要: A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage which can be used to represent information such as binary bits. A control capacitor structure having its first terminal coupled to a first voltage source and its second terminal coupled to the floating gate and a tunneling capacitor structure having its first terminal coupled to a second voltage source and its second terminal coupled to the floating gate are utilized in each embodiment. The control capacitor structure is fabricated so that it has much more capacitance than does the tunneling capacitor structure (and assorted stray capacitance between the floating gate and various other nodes of the cell). Manipulation of the voltages applied to the first voltage source and second voltage source (and Vdd) controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons onto and off of the floating gate, thus controlling the charge on the floating gate and the information value stored thereon.

    摘要翻译: 使用其源极连接到电源(Vdd)的浮栅pFET读出晶体管构造非易失性存储单元,其漏极提供可被感测以确定单元的状态的电流。 pFET读出晶体管的栅极提供电荷存储,可用于表示诸如二进制位之类的信息。 一种控制电容器结构,其第一端耦合到第一电压源,其第二端耦合到浮置栅极,并且隧道电容器结构具有耦合到第二电压源的第一端和其耦合到浮置栅极的第二端。 各实施例。 制造控制电容器结构使得其具有比隧道电容器结构(以及浮动栅极和电池的各种其他节点之间的杂散电容)多得多的电容。 对施加到第一电压源和第二电压源(和Vdd)的电压的操纵控制电容器结构和pFET电介质两端的电场,从而使Fowler-Nordheim将电子隧穿到浮栅上和从浮栅上,从而控制电荷 浮动门和存储在其上的信息值。