公开(公告)号：US20100044805A1

公开(公告)日：2010-02-25

申请号：US12609555

申请日：2009-10-30

申请人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L29/78

CPC分类号： H01L21/28088 ,  H01L21/28518 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

摘要： A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.

摘要翻译： 提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。 本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含金属层的底部至顶部。 通过利用具有小于1.1的金属与氮的组成比的金属含氮层来实现提高的可靠性。 本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。 本发明还提供一种制造这种栅叠层的方法，其中改变溅射工艺的工艺条件以控制溅射沉积层内的金属和氮的比例。

公开(公告)号：US20080191292A1

公开(公告)日：2008-08-14

申请号：US11673901

申请日：2007-02-12

申请人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L29/49 ,  H01L21/3205

CPC分类号： H01L21/28088 ,  H01L21/28518 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

摘要： A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.

摘要翻译： 提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。 本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含金属层的底部至顶部。 通过利用具有小于1.1的金属与氮的组成比的金属含氮层来实现提高的可靠性。 本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。 本发明还提供一种制造这种栅叠层的方法，其中改变溅射工艺的工艺条件以控制溅射沉积层内的金属和氮的比例。

公开(公告)号：US07611979B2

公开(公告)日：2009-11-03

申请号：US11673901

申请日：2007-02-12

申请人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L21/3205 ,  H01L21/28

CPC分类号： H01L21/28088 ,  H01L21/28518 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

摘要： A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.

摘要翻译： 提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。 本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含金属层的底部至顶部。 通过利用具有小于1.1的金属与氮的组成比的金属含氮层来实现提高的可靠性。 本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。 本发明还提供一种制造这种栅叠层的方法，其中改变溅射工艺的工艺条件以控制溅射沉积层内的金属和氮的比例。

公开(公告)号：US20080203485A1

公开(公告)日：2008-08-28

申请号：US11680108

申请日：2007-02-28

申请人： Michael P. Chudzik ,  Wei He ,  Renee T. Mo ,  Naim Moumen ,  Vijay Narayanan ,  Dae-gyu Park ,  Vamsi Paruchuri

发明人： Michael P. Chudzik ,  Wei He ,  Renee T. Mo ,  Naim Moumen ,  Vijay Narayanan ,  Dae-gyu Park ,  Vamsi Paruchuri

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78 ,  H01L29/7845

摘要： A gate structure for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack having a first gate dielectric layer formed over a substrate, and a first metal layer formed over the first gate dielectric layer. A second gate stack includes a second gate dielectric layer formed over the substrate and a second metal layer formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.

摘要翻译： 用于互补金属氧化物半导体（CMOS）器件的栅极结构包括具有形成在衬底上的第一栅极介电层的第一栅极堆叠和形成在第一栅极介电层上的第一金属层。 第二栅极堆叠包括形成在衬底上的第二栅极电介质层和形成在第二栅极介电层上的第二金属层。 第一金属层形成为在基板上施加拉伸应力，并且第二金属层以使得在基板上施加压应力的方式形成。

公开(公告)号：US08507992B2

公开(公告)日：2013-08-13

申请号：US13048170

申请日：2011-03-15

申请人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

发明人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

IPC分类号： H01L21/70

CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/78

摘要： A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.

摘要翻译： 提供一种形成半导体器件的方法，包括在基板的p型器件区域的顶部形成含Ge层。 此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。 然后，栅极结构可以形成在衬底的p型器件区域和n型器件区域的顶部，其中n型器件区域的栅极结构包括稀土金属。

公开(公告)号：US07943460B2

公开(公告)日：2011-05-17

申请号：US12426457

申请日：2009-04-20

申请人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

发明人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/78

摘要： A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.

摘要翻译： 提供一种形成半导体器件的方法，包括在基板的p型器件区域的顶部形成含Ge层。 此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。 然后，栅极结构可以形成在衬底的p型器件区域和n型器件区域的顶部，其中n型器件区域的栅极结构包括稀土金属。

公开(公告)号：US20110156158A1

公开(公告)日：2011-06-30

申请号：US13048170

申请日：2011-03-15

申请人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

发明人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/78

摘要： A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.

摘要翻译： 提供一种形成半导体器件的方法，包括在基板的p型器件区域的顶部形成含Ge层。 此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。 然后，栅极结构可以形成在衬底的p型器件区域和n型器件区域的顶部，其中n型器件区域的栅极结构包括稀土金属。

公开(公告)号：US20100264495A1

公开(公告)日：2010-10-21

申请号：US12426457

申请日：2009-04-20

申请人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

发明人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/78

摘要： A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.

摘要翻译： 提供一种形成半导体器件的方法，包括在基板的p型器件区域的顶部形成含Ge层。 此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。 然后，栅极结构可以形成在衬底的p型器件区域和n型器件区域的顶部，其中n型器件区域的栅极结构包括稀土金属。

公开(公告)号：US20110227171A1

公开(公告)日：2011-09-22

申请号：US13150378

申请日：2011-06-01

申请人： Michael P. Chudzik ,  William K. Henson ,  Renee T. Mo ,  Jeffrey Sleight

发明人： Michael P. Chudzik ,  William K. Henson ,  Renee T. Mo ,  Jeffrey Sleight

IPC分类号： H01L29/51

CPC分类号： H01L29/517 ,  H01L21/28123 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.

摘要翻译： 公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。 栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘 电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。 栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。

公开(公告)号：US20090152650A1

公开(公告)日：2009-06-18

申请号：US11954775

申请日：2007-12-12

申请人： Michael P. Chudzik ,  William K. Henson ,  Renee T. Mo ,  Jeffrey W Sleight

发明人： Michael P. Chudzik ,  William K. Henson ,  Renee T. Mo ,  Jeffrey W Sleight

IPC分类号： H01L29/49 ,  H01L21/283

CPC分类号： H01L29/517 ,  H01L21/28123 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.

摘要翻译： 公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。 栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘 电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。 栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。