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    Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory semiconductor device
    3.
    发明授权
    Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory semiconductor device 有权
    用于0.18微米闪存半导体器件的无空隙层间电介质（ILD0）

    公开(公告)号：US06627973B1

    公开(公告)日：2003-09-30

    申请号：US10244129

    申请日：2002-09-13

    申请人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

    发明人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

    IPC分类号： H01L29167

    CPC分类号： H01L21/02271 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/31625 ,  H01L21/76801

    摘要： A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology. A low dopant/TEOS flow performed at a higher pressure during the deposition of the first layer provides an excellent gap-filling capability which eliminates voiding. Further, the present invention has the advantage of in-situ deposition of the void-free ILD0 layer of the 0.18-&mgr;m flash memory semiconductor device having a sound dopant concentration.

    摘要翻译： 一种消除0.18微米闪速存储器半导体器件的层间电介质材料中的空隙的方法和通过该方法形成的半导体器件。 本发明提供一种通过使用非常低的沉积速率并且具有在约3k范围内的厚度的第一BPTEOS层来消除0.18微米快闪存储器半导体器件的层间电介质中的空隙的方法; 并提供第二BPTEOS层，使用标准沉积速率并且具有在约13k范围内的厚度，其中两层的原子掺杂剂浓度为约4.5％B和约5％P。这两步沉积过程完全 消除了0.5-mum距离（栅极到栅极）的ILD中的空隙以及将来闪存技术的0.38μm距离（栅极到栅极）。 在第一层沉积期间在较高压力下执行的低掺杂剂/ TEOS流提供了优异的间隙填充能力，其消除了排尿。 此外，本发明的优点是具有声掺杂剂浓度的0.18μm的闪存半导体器件的无空隙的ILD0层的原位沉积。

    Method of forming a void-free interlayer dielectric (ILD0) for 0.18-&mgr;m flash memory technology and semiconductor device thereby formed
    4.
    发明授权
    Method of forming a void-free interlayer dielectric (ILD0) for 0.18-&mgr;m flash memory technology and semiconductor device thereby formed 失效
    由此形成用于0.18微米快闪存储器技术的无空隙层间电介质（ILD0）和由此形成的半导体器件的方法

    公开(公告)号：US06489253B1

    公开(公告)日：2002-12-03

    申请号：US09788045

    申请日：2001-02-16

    申请人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

    发明人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

    IPC分类号： H01L21469

    CPC分类号： H01L21/02271 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/31625 ,  H01L21/76801

    摘要： A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology. A low dopant/TEOS flow performed at a higher pressure during the deposition of the first layer provides an excellent gap-filling capability which eliminates voiding. Further, the present invention has the advantage of in-situ deposition of the void-free ILD0 layer of the 0.18-&mgr;m flash memory semiconductor device having a sound dopant concentration.

    摘要翻译： 一种消除0.18微米闪速存储器半导体器件的层间电介质材料中的空隙的方法和通过该方法形成的半导体器件。 本发明提供一种通过使用非常低的沉积速率并且具有在约3k范围内的厚度的第一BPTEOS层来消除0.18微米快闪存储器半导体器件的层间电介质中的空隙的方法; 并提供第二BPTEOS层，使用标准沉积速率并且具有在约13k范围内的厚度，其中两层的原子掺杂剂浓度为约4.5％B和约5％P。这两步沉积过程完全 消除了0.5-mum距离（栅极到栅极）的ILD中的空隙以及将来闪存技术的0.38μm距离（栅极到栅极）。 在第一层沉积期间在较高压力下执行的低掺杂剂/ TEOS流提供了优异的间隙填充能力，其消除了排尿。 此外，本发明的优点是具有声掺杂剂浓度的0.18μm的闪存半导体器件的无空隙的ILD0层的原位沉积。

    Interconnect with multiple layers of conductive material with grain boundary between the layers
    5.
    发明授权
    Interconnect with multiple layers of conductive material with grain boundary between the layers 有权
    与层之间具有晶界的多层导电材料互连

    公开(公告)号：US07001840B1

    公开(公告)日：2006-02-21

    申请号：US10361332

    申请日：2003-02-10

    申请人： Minh Quoc Tran ,  Lu You ,  Fei Wang ,  Lynne Okada

    发明人： Minh Quoc Tran ,  Lu You ,  Fei Wang ,  Lynne Okada

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76879 ,  H01L21/2885

    摘要： An interconnect structure is formed with a plurality of layers of a conductive material with a grain boundary between any two adjacent layers of the conductive material. Such grain boundaries between layers of conductive material act as shunt by-pass paths for migration of atoms of the conductive material to minimize migration of atoms of the conductive material along the interface between a dielectric passivation or capping layer and the interconnect structure. When the interconnect structure is a via structure, each of the layers of the conductive material and each of the grain boundary are formed to be perpendicular to a direction of current flow through the via structure. Such grain boundaries formed between the plurality of layers of conductive material in the via structure minimize charge carrier wind-force along the direction of current flow through the via structure to further minimize electromigration failure of the via structure.

    摘要翻译： 互连结构形成有导电材料的多层，在导电材料的任何两个相邻层之间具有晶界。 导电材料层之间的这种晶界作为用于迁移导电材料的原子的分流旁通路径，以最小化导电材料原子沿着介电钝化层或覆盖层与互连结构之间的界面的迁移。 当互连结构是通孔结构时，导电材料的每个层和每个晶界形成为垂直于通过过孔结构的电流的方向。 在通孔结构中的多个导电材料层之间形成的这种晶界沿着通过通孔结构的电流流动的方向最小化载流子的风力，以进一步最小化通孔结构的电迁移故障。

    Method for forming dual damascene interconnect structure
    6.
    发明授权
    Method for forming dual damascene interconnect structure 有权
    双镶嵌互连结构的形成方法

    公开(公告)号：US06756300B1

    公开(公告)日：2004-06-29

    申请号：US10324259

    申请日：2002-12-18

    申请人： Fei Wang ,  Jerry Cheng ,  Lynne A. Okada ,  Minh Quoc Tran ,  Lu You

    发明人： Fei Wang ,  Jerry Cheng ,  Lynne A. Okada ,  Minh Quoc Tran ,  Lu You

    IPC分类号： H01L214763

    CPC分类号： H01L21/76811 ,  H01L21/76813

    摘要： For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material disposed over the via and trench mask materials. The via and trench mask materials exposed through the via opening of the via mask patterning material are etched away, and the via mask patterning material is etched away. A portion of the dielectric material exposed through the via opening is etched down to the underlying interconnect structure, and a portion of the dielectric material exposed through the trench opening is etched, to form the dual damascene opening.

    摘要翻译： 为了在介电材料内形成双镶嵌开口，在电介质材料上形成通孔掩模材料和沟槽掩模材料。 通过沟槽掩模材料形成沟槽开口，并且通过布置在通孔和沟槽掩模材料上方的通孔掩模图案形成材料形成通孔开口。 通过通孔掩模图形材料的通路孔露出的通孔和沟槽掩模材料被蚀刻掉，并且通孔掩模图案材料被蚀刻掉。 通过通孔开口暴露的介电材料的一部分被蚀刻到下面的互连结构上，并且蚀刻通过沟槽开口露出的电介质材料的一部分，以形成双镶嵌开口。

    Ultra low dielectric constant integrated circuit system
    7.
    发明授权
    Ultra low dielectric constant integrated circuit system 有权
    超低介电常数集成电路系统

    公开(公告)号：US07256499B1

    公开(公告)日：2007-08-14

    申请号：US11230985

    申请日：2005-09-19

    申请人： Lu You ,  Fei Wang ,  Minh Quoc Tran ,  Lynne A. Okada

    发明人： Lu You ,  Fei Wang ,  Minh Quoc Tran ,  Lynne A. Okada

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit is provided including forming a porous ultra-low dielectric constant dielectric layer over a semiconductor substrate and forming an opening in the ultra-low dielectric constant dielectric layer. A dielectric liner is formed to line the opening to cover the pores in the ultra-low dielectric constant dielectric layer and a barrier layer is deposited to line the dielectric liner and conductor core is deposited to fill the opening over the barrier layer.

    摘要翻译： 提供了一种集成电路，包括在半导体衬底上形成多孔超低介电常数介电层，并在超低介电常数介电层中形成开口。 形成电介质衬垫以使开口线对，以覆盖超低介电常数电介质层中的孔，并且沉积阻挡层以对电介质衬垫进行排列，并且沉积导体芯以填充阻挡层上的开口。

    Sealing sidewall pores in low-k dielectrics
    8.
    发明授权
    Sealing sidewall pores in low-k dielectrics 有权
    密封低k电介质中的侧壁孔

    公开(公告)号：US07208418B1

    公开(公告)日：2007-04-24

    申请号：US10728774

    申请日：2003-12-08

    申请人： Lynne A. Okada ,  Minh Quoc Tran ,  Fei Wang ,  Lu You

    发明人： Lynne A. Okada ,  Minh Quoc Tran ,  Fei Wang ,  Lu You

    IPC分类号： H01L21/311

    CPC分类号： H01L21/76831

    摘要： Barrier metal layer discontinuities or gaps due to low-k dielectric porosity is reduced by sealing sidewall porosity before barrier metal layer deposition. Embodiments include sealing sidewall porosity by depositing a swelling agent, adhesion promoter or an additional layer of low-k material.

    摘要翻译： 通过在阻挡金属层沉积之前密封侧壁孔隙率来减少由于低k介电孔隙导致的阻挡金属层不连续性或间隙。 实施例包括通过沉积溶胀剂，粘合促进剂或低k材料的附加层来密封侧壁孔隙。

    Conformal liner for gap-filling
    10.
    发明申请
    Conformal liner for gap-filling 审中-公开
    用于间隙填充的保形衬套

    公开(公告)号：US20080096364A1

    公开(公告)日：2008-04-24

    申请号：US11582442

    申请日：2006-10-18

    申请人： Erik Wilson ,  Minh-Van Ngo ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

    发明人： Erik Wilson ,  Minh-Van Ngo ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823468 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823437

    摘要： Gap filling between features which are closely spaced is significantly improved by initially depositing a thin conformal layer followed by depositing a layer of gap filling dielectric material. Embodiments include depositing a thin conformal layer of silicon nitride or silicon oxide, as by atomic layer deposition or pulsed layer deposition, into the gap between adjacent gate electrode structures such that it flows into undercut regions of dielectric spacers on side surfaces of the gate electrode structures, and then depositing a layer of BPSG or P-HDP oxide on the thin conformal layer into the gap. Embodiments further include depositing the layers at a temperature less than 430° C., as by depositing a P-HDP oxide after depositing the conformal liner when the gate electrode structures include a layer of nickel silicide.

    摘要翻译： 通过初始沉积薄的共形层，然后沉积一层间隙填充电介质材料，密切间隔的特征之间的间隙填充显着改善。 实施例包括通过原子层沉积或脉冲层沉积将氮化硅或氧化硅的薄保形层沉积到相邻栅电极结构之间的间隙中，使得其流到栅电极结构的侧表面上的电介质间隔物的底切区域 ，然后在薄的共形层上沉积一层BPSG或P-HDP氧化物到间隙中。 实施例还包括在低于430℃的温度下沉积层，如通过在栅极电极结构包括硅化镍层沉积保形衬垫之后沉积P-HDP氧化物。