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公开(公告)号：US20120153300A1
公开(公告)日：2012-06-21
申请号：US13325735
申请日：2011-12-14
申请人： Alexander Lidow , Jianjun Cao , Robert Beach , Johan Strydom , Alana Nakata , Guang Y. Zhao
发明人： Alexander Lidow , Jianjun Cao , Robert Beach , Johan Strydom , Alana Nakata , Guang Y. Zhao
CPC分类号： H01L21/743 , H01L21/761 , H01L21/76283 , H01L21/8252 , H01L21/8258 , H01L23/535 , H01L27/0605 , H01L27/0688 , H01L27/085 , H01L29/1075 , H01L29/2003 , H01L29/41766 , H01L29/732 , H01L29/7786 , H01L29/7787 , H01L29/7827 , H01L29/88 , H01L2924/0002 , H01L2924/00
摘要： Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.
摘要翻译： 用于将半导体器件的一部分中的周围材料独立地连接到其相应器件的触点的电路，结构和技术。 为了实现这一点，提供了以至少一个偏置极性电隔离的一个或多个导电阱的组合。
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公开(公告)号：US09607876B2
公开(公告)日：2017-03-28
申请号：US13325735
申请日：2011-12-14
申请人： Alexander Lidow , Jianjun Cao , Robert Beach , Johan Strydom , Alana Nakata , Guang Y. Zhao
发明人： Alexander Lidow , Jianjun Cao , Robert Beach , Johan Strydom , Alana Nakata , Guang Y. Zhao
IPC分类号： H01L21/74 , H01L21/761 , H01L21/762 , H01L29/732 , H01L29/778 , H01L21/8252 , H01L21/8258 , H01L27/06 , H01L27/085 , H01L29/20
CPC分类号： H01L21/743 , H01L21/761 , H01L21/76283 , H01L21/8252 , H01L21/8258 , H01L23/535 , H01L27/0605 , H01L27/0688 , H01L27/085 , H01L29/1075 , H01L29/2003 , H01L29/41766 , H01L29/732 , H01L29/7786 , H01L29/7787 , H01L29/7827 , H01L29/88 , H01L2924/0002 , H01L2924/00
摘要： Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.
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公开(公告)号：US08587274B2
公开(公告)日：2013-11-19
申请号：US12561912
申请日：2009-09-17
申请人： Johan Strydom , Yiding (Eric) Gu
发明人： Johan Strydom , Yiding (Eric) Gu
IPC分类号： G05F1/40
CPC分类号： H02M3/158
摘要： A current mode power conversion system and method are described that provide a stable output voltage and a maximum-limited output current to a load. The system comprises: a feedback control linearly operable so as to control the output voltage across the load during constant load conditions, and non-linearly operable so as to control the output voltage across the load during certain detected changes in load conditions above a predetermined threshold so as to speed up the transient response of the power conversion system.
摘要翻译： 描述了向负载提供稳定的输出电压和最大限制的输出电流的电流模式功率转换系统和方法。 该系统包括：线性可操作的反馈控制，以便在恒定负载条件期间控制跨过负载的输出电压，并且非线性地操作，以便在负载状态的某些检测到的变化高于预定阈值时控制负载两端的输出电压 以加快电力转换系统的瞬态响应。
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4.发明授权Test arrangement including anisotropic conductive film for testing power module 有权包括用于测试电源模块的各向异性导电膜的测试布置公开(公告)号：US07355431B2
公开(公告)日：2008-04-08
申请号：US11141860
申请日：2005-06-01
IPC分类号： G01R31/26
CPC分类号： G01R1/0735
摘要： A testing apparatus and method for testing a semiconductor device, and more particularly a test arrangement for measuring a guaranteed power loss of a semiconductor module, not requiring the module to have on-board decoupling capacitors for the power loss test. The conventional pogo-pin array and test socket are replaced by a novel low cost anisotropic conductive elastomer and a low cost socket, the conductive polymer providing electrical communication between the socket and the module under test.
摘要翻译： 一种用于测试半导体器件的测试装置和方法，更具体地，用于测量半导体模块的有保证的功率损耗的测试装置，不需要该模块具有用于功率损耗测试的板载去耦电容器。 常规的弹簧针阵列和测试插座由新颖的低成本各向异性导电弹性体和低成本插座代替，导电聚合物在插座和被测模块之间提供电气连接。
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公开(公告)号：US20110062929A1
公开(公告)日：2011-03-17
申请号：US12561912
申请日：2009-09-17
申请人： Johan Strydom , Yiding (Eric) Gu
发明人： Johan Strydom , Yiding (Eric) Gu
IPC分类号： G05F1/10
CPC分类号： H02M3/158
摘要： A current mode power conversion system and method are described that provide a stable output voltage and a maximum-limited output current to a load. The system comprises: a feedback control linearly operable so as to control the output voltage across the load during constant load conditions, and non-linearly operable so as to control the output voltage across the load during certain detected changes in load conditions above a predetermined threshold so as to speed up the transient response of the power conversion system.
摘要翻译： 描述了向负载提供稳定的输出电压和最大限制的输出电流的电流模式功率转换系统和方法。 该系统包括：线性可操作的反馈控制，以便在恒定负载条件期间控制跨过负载的输出电压，并且非线性地操作，以便在负载状态的某些检测到的变化高于预定阈值时控制负载两端的输出电压 以加快电力转换系统的瞬态响应。
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6.发明申请Test arrangement including anisotropic conductive film for testing power module 有权包括用于测试电源模块的各向异性导电膜的测试布置公开(公告)号：US20050270057A1
公开(公告)日：2005-12-08
申请号：US11141860
申请日：2005-06-01
CPC分类号： G01R1/0735
摘要： A testing apparatus and method for testing a semiconductor device, and more particularly a test arrangement for measuring a guaranteed power loss of a semiconductor module, not requiring the module to have on-board decoupling capacitors for the power loss test. The conventional pogo-pin array and test socket are replaced by a novel low cost anisotropic conductive elastomer and a low cost socket, the conductive polymer providing electrical communication between the socket and the module under test.
摘要翻译： 一种用于测试半导体器件的测试装置和方法，更具体地，用于测量半导体模块的有保证的功率损耗的测试装置，不需要该模块具有用于功率损耗测试的板载去耦电容器。 常规的弹簧针阵列和测试插座由新颖的低成本各向异性导电弹性体和低成本插座代替，导电聚合物在插座和被测模块之间提供电气连接。
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公开(公告)号：US09331061B2
公开(公告)日：2016-05-03
申请号：US13596962
申请日：2012-08-28
申请人： Michael A. De Rooij , Johan Strydom
发明人： Michael A. De Rooij , Johan Strydom
IPC分类号： H03K17/12 , H01L27/02 , H01L27/082 , H01L27/085
CPC分类号： H01L27/0207 , H01L27/082 , H01L27/085 , H03K17/122
摘要： Parallel transistor circuits with reduced effects from common source induction. The parallel transistors include physical gate connections that are located electrically close to one another. The parallel circuits are arranged such that the voltage at the common gate connection resulting from transient currents across common source inductance is substantially balanced. The circuits include switching circuits, converters, and RF amplifiers.
摘要翻译： 并联晶体管电路具有从普通源极感应效应降低的效果。 并联晶体管包括物理栅极连接，这些物理栅极连接彼此电气靠近。 并联电路被布置成使得由跨过公共源电感的瞬态电流产生的公共栅极连接处的电压基本上是平衡的。 电路包括开关电路，转换器和RF放大器。
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公开(公告)号：US20130049814A1
公开(公告)日：2013-02-28
申请号：US13596962
申请日：2012-08-28
申请人： Michael A. De Rooij , Johan Strydom
发明人： Michael A. De Rooij , Johan Strydom
IPC分类号： H03K3/00 , H01L21/335
CPC分类号： H01L27/0207 , H01L27/082 , H01L27/085 , H03K17/122
摘要： Parallel transistor circuits with reduced effects from common source induction. The parallel transistors include physical gate connections that are located electrically close to one another. The parallel circuits are arranged such that the voltage at the common gate connection resulting from transient currents across common source inductance is substantially balanced. The circuits include switching circuits, converters, and RF amplifiers.
摘要翻译： 并联晶体管电路具有从普通源极感应效应降低的效果。 并联晶体管包括物理栅极连接，这些物理栅极连接彼此电气靠近。 并联电路被布置成使得由跨过公共源电感的瞬态电流产生的公共栅极连接处的电压基本上是平衡的。 电路包括开关电路，转换器和RF放大器。
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