-
1.发明授权
公开(公告)号：US5255374A
公开(公告)日：1993-10-19
申请号：US816203
申请日：1992-01-02
CPC分类号： G06F13/1684
摘要： A computer system is provided, comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to an input/output device by an input/output bus. The bus interface unit includes translation logic for temporarily storing, in response to a predetermined set of operating conditions, data transferred between the system bus and the input/output bus through the bus interface unit. The predetermined set of operating conditions occur when (i) the memory controller on behalf of the central processing unit writes data to the input/output device, or (ii) the memory controller on behalf of the central processing unit initiates a read or write cycle destined for the input/output device acting as a slave on the input/output bus, and the data bus width of the memory controller is greater than a corresponding data bus width of the input/output device.
-
2.发明授权System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus 失效系统具有总线接口单元，用于在系统资源设备已经获得总线控制之后超越正常的仲裁方案
公开(公告)号：US5544346A
公开(公告)日：1996-08-06
申请号：US353165
申请日：1994-12-09
CPC分类号： G06F13/1605
摘要： An information handling systems capable of transferring data among various system resource devices such as input/output (I/O) devices and a system memory includes a first bus coupled to the system memory, a second bus coupled to the system resource devices, and a bus interface unit (BIU) coupled between the first bus and the second bus. Each of the system resource devices is capable of controlling the second bus after arbitrating therefor. The BIU includes a buffer for temporary storage of data being transferred between the first bus and the second bus, and control logic for generating a lock control signal, after one of the system resource devices has gained control of the second bus by arbitration, to gain control of the first bus to prevent other system resource devices from accessing the first bus. The control signal is dynamically generated by the BIU based on programmable conditions relating to the data transfer, thus optimizing data transfers between the first bus and the second bus. The control signal may act as an override to the normal memory controller arbitration scheme to prioritize access of the system resource devices to the system memory.
摘要翻译： 能够在诸如输入/输出（I / O）设备和系统存储器的各种系统资源设备之间传送数据的信息处理系统包括耦合到系统存储器的第一总线，耦合到系统资源设备的第二总线，以及 总线接口单元（BIU），耦合在第一总线和第二总线之间。 每个系统资源设备在对其进行仲裁之后能够控制第二总线。 BIU包括用于临时存储在第一总线和第二总线之间传输的数据的缓冲器，以及用于在系统资源设备之一通过仲裁获得第二总线的控制之后产生锁定控制信号的控制逻辑，以获得 控制第一总线以防止其他系统资源设备访问第一总线。 基于与数据传输相关的可编程条件，BIU动态地产生控制信号，从而优化第一总线与第二总线之间的数据传输。 控制信号可以作为对正常存储器控制器仲裁方案的覆盖，以优先考虑系统资源设备对系统存储器的访问。
-
3.发明授权
公开(公告)号：US5265211A
公开(公告)日：1993-11-23
申请号：US816116
申请日：1992-01-02
IPC分类号： G06F13/28 , G06F13/22 , G06F13/36 , G06F13/362
CPC分类号： G06F13/225 , G06F13/362
摘要： A computer system is provided comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to a plurality of input/output devices by an input/output bus. The bus interface unit is able to sense when said one of said input/output devices has completed a read or write operation over said input/output bus, and includes a buffer circuit wherein read and write data transferred between the system bus and the input/output bus via the bus interface unit is temporarily stored during the transfer. Arbitration control logic resides in said bus interface unit and interacts with a central arbitration controller which resides on the system bus. The central arbitration controller responds to the arbitration control logic to simultaneously perform (i) arbitration cycles wherein the central arbitration controller arbitrates between the plurality of input/output devices and the central processing unit to determine which of the input/output devices or the central processing unit should be granted control of the input/output bus and (ii) grant cycles wherein the central arbitration controller grants control of the input/output bus and extends control of the system bus to one of the input/output devices or the central processing unit.
-
公开(公告)号：US5333274A
公开(公告)日：1994-07-26
申请号：US778040
申请日：1991-10-15
CPC分类号： G06F13/28 , G06F11/00 , G06F11/0751 , G06F11/0757 , G06F11/0763 , G06F11/1402
摘要： A DMA controller with error circuitry which detects DMA error conditions is disclosed. The error circuitry causes the DMA controller to perform completion tasks before terminating a DMA transfer, advantageously providing a DMA controller which may exit gracefully upon detection of an error condition with the potential of error recovery.
摘要翻译： 公开了一种具有检测DMA错误状况的错误电路的DMA控制器。 错误电路使得DMA控制器在终止DMA传输之前执行完成任务，有利地提供了一个DMA控制器，它可以在检测到具有错误恢复潜力的错误状况时正常地退出。
-
5.发明授权System direct memory access (DMA) support logic for PCI based computer system 失效用于基于PCI的计算机系统的系统直接存储器访问（DMA）支持逻辑
公开(公告)号：US5450551A
公开(公告)日：1995-09-12
申请号：US68477
申请日：1993-05-28
IPC分类号： G06F13/28 , G06F13/30 , G06F13/36 , G06F13/40 , G06F13/364
CPC分类号： G06F13/4018 , G06F13/30 , G06F13/36
摘要： A direct memory access (DMA) support mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU) connected to system memory by a first system bus, and a second system bus connected to the CPU; (ii) a host bridge connecting the second system bus to a peripheral bus; (iii) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto; and (v) arbitration logic which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.
摘要翻译： 提供直接存储器访问（DMA）支持机制用于计算机系统，其包括（i）通过第一系统总线连接到系统存储器的中央处理单元（CPU）和连接到CPU的第二系统总线; （ii）将第二系统总线连接到外围总线的主桥; （iii）将外围总线连接到标准I / O总线的输入/输出（I / O）桥，标准I / O总线具有连接到其上的多个标准I / O设备; 以及（v）以仲裁模式起作用的仲裁逻辑，用于在竞争访问标准I / O总线的多个标准I / O设备之间进行仲裁，并且在授权模式中，授权选择的标准I / O设备被授权访问 到标准I / O总线。 DMA支持机制包括代表所选标准I / O设备执行DMA周期的直接存储器访问（DMA）控制器，以及直接存储器访问（DMA）支持逻辑，用于通过外设总线执行DMA周期。 DMA支持逻辑包括直接连接DMA控制器与I / O桥的边带信号，边带信号包括识别DMA控制器正在执行DMA周期的所选I / O设备的总线大小的信息。
-
6.发明授权Computer system with varied data transfer speeds between system components and memory 失效计算机系统在系统组件和内存之间具有不同的数据传输速度
公开(公告)号：US5761533A
公开(公告)日：1998-06-02
申请号：US293411
申请日：1994-08-19
申请人： Alfredo Aldereguia , Nader Amini , Daryl Carvis Cromer , Richard Louis Horne , Ashu Kohli , Kimberly Kibbe Sendlein , Cang Ngoc Tran
发明人： Alfredo Aldereguia , Nader Amini , Daryl Carvis Cromer , Richard Louis Horne , Ashu Kohli , Kimberly Kibbe Sendlein , Cang Ngoc Tran
CPC分类号： G06F13/1689
摘要： A computer system is provided, comprising system memory and a memory controller which resides on a system bus for controlling access to the system memory, a bus interface unit and a direct memory access controller also residing on the system bus, and a central processing unit electrically connected with the memory controller which is able to read and write data to the system memory via the memory controller. The memory controller and the bus interface unit each operate, when either is in control of the system bus, at a clock frequency which is a multiple of the clock frequency at which the direct memory access controller operates on the system bus. The memory controller and the bus interface unit each operate, when the direct memory access controller is in control of the system bus, at the same clock frequency as that of the direct memory access controller. The clock frequencies of the memory controller, the bus interface unit and the direct memory access controller are each synchronized in time. The computer system thereby permits system bus devices, operating at different clock frequencies, to coexist on the system bus without hindering the performance of the faster speed devices.
摘要翻译： 提供了一种计算机系统，包括系统存储器和驻留在用于控制对系统存储器的访问的系统总线上的存储器控制器，总线接口单元和也驻留在系统总线上的直接存储器访问控制器，以及电子 与能够通过存储器控制器将数据读取和写入系统存储器的存储器控制器连接。 当存储器控制器和总线接口单元在控制系统总线时都以在直接存储器访问控制器在系统总线上操作的时钟频率的倍数的时钟频率下操作。 当直接存储器存取控制器处于系统总线的控制状态时，存储器控制器和总线接口单元在与直接存储器存取控制器相同的时钟频率下操作。 存储器控制器，总线接口单元和直接存储器访问控制器的时钟频率各自在时间上同步。 因此，计算机系统允许以不同时钟频率工作的系统总线设备在系统总线上共存而不会妨碍更快速的设备的性能。
-
7.发明授权Expandable high performance FIFO design which includes memory cells having respective cell multiplexors 失效可扩展的高性能FIFO设计，其包括具有相应的单元复用器的存储单元
公开(公告)号：US5551009A
公开(公告)日：1996-08-27
申请号：US134504
申请日：1993-10-12
CPC分类号： G06F5/065
摘要： An arrangement of cells with input and output steering circuitry as well as internal shifting capabilities is disclosed which advantageously provides a first in/first out (FIFO) register circuit which can be written to and read from in contiguous clock cycles. The FIFO register circuit is provided with an arrangement of self contained FIFO cells, each cell containing its own input multiplexer and control circuitry.
摘要翻译： 公开了具有输入和输出转向电路以及内部移位能力的单元的布置，其有利地提供可以连续的时钟周期写入和读取的第一进/出（FIFO）寄存器电路。 FIFO寄存器电路具有自包含FIFO单元的布置，每个单元包含其自己的输入多路复用器和控制电路。
-
公开(公告)号：US5548786A
公开(公告)日：1996-08-20
申请号：US224123
申请日：1994-04-06
申请人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Ian A. Concilio , Richard G. Hofmann , Terence J. Lohman
发明人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Ian A. Concilio , Richard G. Hofmann , Terence J. Lohman
CPC分类号： G06F13/28
摘要： A DMA controller is provided for transferring data between source and destination devices over an I/O bus. The DMA control circuit includes a bus interface unit for providing a bus size information at the beginning of each consecutive bus cycle and a look ahead responsive to the bus size information for providing a bus size control signal. A DMA control circuit responsive to the bus size control signal controls the bus width during contiguous transfer cycles. By dynamically adjusting the DMA control circuit, back to back data reads and writes may occur with no wait states inserted for generating the terminal count information.
摘要翻译： 提供DMA控制器用于通过I / O总线在源设备和目标设备之间传输数据。 DMA控制电路包括总线接口单元，用于在每个连续的总线周期的开始处提供总线尺寸信息，并且响应于总线尺寸信息提供前视，用于提供总线尺寸控制信号。 响应于总线尺寸控制信号的DMA控制电路在连续传送周期期间控制总线宽度。 通过动态调整DMA控制电路，背靠背数据读取和写入可能会在没有插入等待状态以产生终端计数信息的情况下进行。
-
公开(公告)号：US5396602A
公开(公告)日：1995-03-07
申请号：US69253
申请日：1993-05-28
IPC分类号： G06F13/36 , G06F13/362 , G06F13/364 , G06F13/40
CPC分类号： G06F13/364 , G06F13/4031
摘要： An arbitration mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU); (ii) a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; (iii) a second system bus connected to the CPU; (iv) a host bridge connecting the second system bus to a peripheral bus, the peripheral bus having at least one peripheral device attached thereto; and (v) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto. The arbitration mechanism comprises (i) a first level of logic for arbitrating between the plurality of standard I/O devices, wherein one standard I/O device is selected from a plurality of the standard I/O devices competing for access to the standard I/O bus, and (ii) a second level of logic for arbitrating between the selected standard I/O device, the CPU and the at least one peripheral device, wherein one of the selected standard I/O device, the CPU and the at least one peripheral device is selected to access the peripheral bus. The arbitration mechanism includes sideband signals which connect the first and second levels of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device.
摘要翻译： 提供了一种在计算机系统中使用的仲裁机制，其包括（i）中央处理单元（CPU）; （ii）第一系统总线，其将CPU连接到系统存储器，使得CPU可以从系统存储器读取数据并将数据写入系统存储器; （iii）连接到CPU的第二系统总线; （iv）将所述第二系统总线连接到外围总线的主桥，所述外围总线具有附接到其上的至少一个外围设备; 以及（v）将外围总线连接到标准I / O总线的输入/输出（I / O）桥，所述标准I / O总线具有附接到其上的多个标准I / O设备。 仲裁机制包括（i）用于在多个标准I / O设备之间进行仲裁的第一级逻辑，其中从多个标准I / O设备中选择一个标准I / O设备来竞争访问标准I / O总线，以及（ii）用于在所选择的标准I / O设备，CPU和至少一个外围设备之间进行仲裁的第二级逻辑，其中所选择的标准I / O设备，CPU和at 选择至少一个外围设备来访问外围总线。 仲裁机制包括连接第一级仲裁逻辑和第二级仲裁逻辑的边带信号，并包括对应于所选标准I / O设备的仲裁识别信息。
-
10.发明授权DMA controller including a FIFO register and a residual register for data buffering and having different operating modes 失效DMA控制器包括FIFO寄存器和用于数据缓冲的残留寄存器，并具有不同的工作模式
公开(公告)号：US5381538A
公开(公告)日：1995-01-10
申请号：US778042
申请日：1991-10-15
申请人： Nader Amini , Bechara F. Boury , Terence J. Lohman
发明人： Nader Amini , Bechara F. Boury , Terence J. Lohman
CPC分类号： G06F13/28
摘要： A direct memory access (DMA) controller for exchanging data information between a system memory and an input/output (I/O) device in an initial data exchange mode and an alternate data exchange mode includes a register for exchanging the data information during both modes and a residual data register for storing residual data information in the register upon commencement of the alternate data exchange mode and for providing the residual data information when the initial data exchange mode is restarted.
摘要翻译： 用于在初始数据交换模式和备用数据交换模式下在系统存储器和输入/输出（I / O）设备之间交换数据信息的直接存储器访问（DMA）控制器包括用于在两种模式下交换数据信息的寄存器 以及剩余数据寄存器，用于在备用数据交换模式开始时将剩余数据信息存储在寄存器中，并且用于当初始数据交换模式重新启动时提供残留数据信息。
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.027 秒)
