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    Dynamic bus sizing of DMA transfers
    2.
    发明授权
    Dynamic bus sizing of DMA transfers 失效
    DMA传输的动态总线大小

    公开(公告)号：US5548786A

    公开(公告)日：1996-08-20

    申请号：US224123

    申请日：1994-04-06

    申请人： Nader Amini ,  Bechara F. Boury ,  Sherwood Brannon ,  Ian A. Concilio ,  Richard G. Hofmann ,  Terence J. Lohman

    发明人： Nader Amini ,  Bechara F. Boury ,  Sherwood Brannon ,  Ian A. Concilio ,  Richard G. Hofmann ,  Terence J. Lohman

    IPC分类号： G06F13/28 ,  G06F13/00 ,  G06F13/40

    CPC分类号： G06F13/28

    摘要： A DMA controller is provided for transferring data between source and destination devices over an I/O bus. The DMA control circuit includes a bus interface unit for providing a bus size information at the beginning of each consecutive bus cycle and a look ahead responsive to the bus size information for providing a bus size control signal. A DMA control circuit responsive to the bus size control signal controls the bus width during contiguous transfer cycles. By dynamically adjusting the DMA control circuit, back to back data reads and writes may occur with no wait states inserted for generating the terminal count information.

    摘要翻译： 提供DMA控制器用于通过I / O总线在源设备和目标设备之间传输数据。 DMA控制电路包括总线接口单元，用于在每个连续的总线周期的开始处提供总线尺寸信息，并且响应于总线尺寸信息提供前视，用于提供总线尺寸控制信号。 响应于总线尺寸控制信号的DMA控制电路在连续传送周期期间控制总线宽度。 通过动态调整DMA控制电路，背靠背数据读取和写入可能会在没有插入等待状态以产生终端计数信息的情况下进行。

    System direct memory access (DMA) support logic for PCI based computer system
    3.
    发明授权
    System direct memory access (DMA) support logic for PCI based computer system 失效
    用于基于PCI的计算机系统的系统直接存储器访问（DMA）支持逻辑

    公开(公告)号：US5450551A

    公开(公告)日：1995-09-12

    申请号：US68477

    申请日：1993-05-28

    申请人： Nader Amini ,  Patrick M. Bland ,  Bechara F. Boury ,  Richard G. Hofmann ,  Terence J. Lohman

    发明人： Nader Amini ,  Patrick M. Bland ,  Bechara F. Boury ,  Richard G. Hofmann ,  Terence J. Lohman

    IPC分类号： G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/40 ,  G06F13/364

    CPC分类号： G06F13/4018 ,  G06F13/30 ,  G06F13/36

    摘要： A direct memory access (DMA) support mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU) connected to system memory by a first system bus, and a second system bus connected to the CPU; (ii) a host bridge connecting the second system bus to a peripheral bus; (iii) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto; and (v) arbitration logic which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.

    摘要翻译： 提供直接存储器访问（DMA）支持机制用于计算机系统，其包括（i）通过第一系统总线连接到系统存储器的中央处理单元（CPU）和连接到CPU的第二系统总线; （ii）将第二系统总线连接到外围总线的主桥; （iii）将外围总线连接到标准I / O总线的输入/输出（I / O）桥，标准I / O总线具有连接到其上的多个标准I / O设备; 以及（v）以仲裁模式起作用的仲裁逻辑，用于在竞争访问标准I / O总线的多个标准I / O设备之间进行仲裁，并且在授权模式中，授权选择的标准I / O设备被授权访问 到标准I / O总线。 DMA支持机制包括代表所选标准I / O设备执行DMA周期的直接存储器访问（DMA）控制器，以及直接存储器访问（DMA）支持逻辑，用于通过外设总线执行DMA周期。 DMA支持逻辑包括直接连接DMA控制器与I / O桥的边带信号，边带信号包括识别DMA控制器正在执行DMA周期的所选I / O设备的总线大小的信息。

    Arbitration logic for multiple bus computer system
    4.
    发明授权
    Arbitration logic for multiple bus computer system 失效
    多总线计算机系统的仲裁逻辑

    公开(公告)号：US5396602A

    公开(公告)日：1995-03-07

    申请号：US69253

    申请日：1993-05-28

    申请人： Nader Amini ,  Patrick M. Bland ,  Bechara F. Boury ,  Richard G. Hofmann ,  Terence J. Lohman

    发明人： Nader Amini ,  Patrick M. Bland ,  Bechara F. Boury ,  Richard G. Hofmann ,  Terence J. Lohman

    IPC分类号： G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/40

    CPC分类号： G06F13/364 ,  G06F13/4031

    摘要： An arbitration mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU); (ii) a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; (iii) a second system bus connected to the CPU; (iv) a host bridge connecting the second system bus to a peripheral bus, the peripheral bus having at least one peripheral device attached thereto; and (v) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto. The arbitration mechanism comprises (i) a first level of logic for arbitrating between the plurality of standard I/O devices, wherein one standard I/O device is selected from a plurality of the standard I/O devices competing for access to the standard I/O bus, and (ii) a second level of logic for arbitrating between the selected standard I/O device, the CPU and the at least one peripheral device, wherein one of the selected standard I/O device, the CPU and the at least one peripheral device is selected to access the peripheral bus. The arbitration mechanism includes sideband signals which connect the first and second levels of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device.

    摘要翻译： 提供了一种在计算机系统中使用的仲裁机制，其包括（i）中央处理单元（CPU）; （ii）第一系统总线，其将CPU连接到系统存储器，使得CPU可以从系统存储器读取数据并将数据写入系统存储器; （iii）连接到CPU的第二系统总线; （iv）将所述第二系统总线连接到外围总线的主桥，所述外围总线具有附接到其上的至少一个外围设备; 以及（v）将外围总线连接到标准I / O总线的输入/输出（I / O）桥，所述标准I / O总线具有附接到其上的多个标准I / O设备。 仲裁机制包括（i）用于在多个标准I / O设备之间进行仲裁的第一级逻辑，其中从多个标准I / O设备中选择一个标准I / O设备来竞争访问标准I / O总线，以及（ii）用于在所选择的标准I / O设备，CPU和至少一个外围设备之间进行仲裁的第二级逻辑，其中所选择的标准I / O设备，CPU和at 选择至少一个外围设备来访问外围总线。 仲裁机制包括连接第一级仲裁逻辑和第二级仲裁逻辑的边带信号，并包括对应于所选标准I / O设备的仲裁识别信息。

    Power management of DMA slaves with DMA traps
    5.
    发明授权
    Power management of DMA slaves with DMA traps 失效
    具有DMA陷阱的DMA从站的电源管理

    公开(公告)号：US5619729A

    公开(公告)日：1997-04-08

    申请号：US584805

    申请日：1996-01-11

    申请人： Patrick M. Bland ,  Richard G. Hofmann ,  Robert T. Jackson ,  Nader Amini ,  Bechara F. Boury ,  Jayesh Joshi

    发明人： Patrick M. Bland ,  Richard G. Hofmann ,  Robert T. Jackson ,  Nader Amini ,  Bechara F. Boury ,  Jayesh Joshi

    IPC分类号： G06F1/32 ,  G06F13/28 ,  G06F13/00

    CPC分类号： G06F1/3225 ,  G06F1/3275 ,  G06F13/28 ,  Y02B60/1225 ,  Y02B60/1228

    摘要： A device and method for power management of direct memory access ("DMA") slaves through DMA traps. The device comprises a plurality of registers coupled with conventional logic in order to generate a control signal for disabling direct memory access transfer requests for a powered-off DMA slave until the slave is re-powered. The method for managing power comprises steps of unmasking bits in a register containing information regarding which DMA slaves have been powered-off. Next, the DMA Controller consults a power management macro ("PMM") to determine whether a DMA transfer request involves a powered-off DMA slave. If not, the DMA transfer continues. However, if the DMA transfer does involve a powered-off DMA slave, then a main software application in operation is temporarily halted and the PMM generates a SMI signal and outputs the SMI signal to the central processing unit ("CPU") while keeping the disable control signal asserted, which effectively disables the DMA channel. The SMI signal invokes a software service routine which re-powers the powered-off DMA slave so that the main software application can continue.

    摘要翻译： 通过DMA陷阱对直接存储器访问（“DMA”）从站进行电源管理的设备和方法。 该装置包括与常规逻辑耦合的多个寄存器，以便产生一个控制信号，用于禁用关闭DMA从器件的直接存储器访问传输请求，直到从器件被重新供电为止。 用于管理功率的方法包括以下步骤：在包含关于哪个DMA从设备已断电的信息的寄存器中取消屏蔽位。 接下来，DMA控制器查询电源管理宏（“PMM”）以确定DMA传输请求是否涉及关闭的DMA从机。 否则，DMA传输继续。 然而，如果DMA传输确实涉及关闭的DMA从器件，则暂时停止正在运行的主要软件应用程序，并且PMM生成SMI信号并将SMI信号输出到中央处理器（“CPU”），同时保持 禁用控制信号有效，从而有效地禁用DMA通道。 SMI信号调用一个软件服务程序，重新供电关闭的DMA从站，使主软件应用程序能够继续运行。

    Single request data transfer regardless of size and alignment
    6.
    发明授权
    Single request data transfer regardless of size and alignment 失效
    单个请求数据传输，无论大小和对齐方式

    公开(公告)号：US07093058B2

    公开(公告)日：2006-08-15

    申请号：US11246427

    申请日：2005-10-07

    申请人： Victor R. Angsburg ,  James N. Dieffenderfer ,  Bernard C. Drerup ,  Richard G. Hofmann ,  Thomas A. Sartorius ,  Barry J. Wolford

    发明人： Victor R. Angsburg ,  James N. Dieffenderfer ,  Bernard C. Drerup ,  Richard G. Hofmann ,  Thomas A. Sartorius ,  Barry J. Wolford

    IPC分类号： G06F13/40 ,  H04L12/56

    CPC分类号： G06F13/4204 ,  Y02D10/14 ,  Y02D10/151

    摘要： A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a starting byte address of the data transfer; a second signal including a size of the data transfer in data beats; and a third signal including a byte enable for each byte required during a last data beat of the data transfer. The invention is usable with single or multiple beat, aligned or unaligned data transfers. Usage of the three transfer qualifier signals provides the slave with how many data beats it will transfer at the start of the transfer, and the alignment of both the starting and ending data beats. As a result, the slave need not calculate the number of bytes it will transfer. In terms of multiple beat transfers, the number of data transfer requests are reduced, which reduces the amount of switching, bus arbitration and power consumption required. In addition, the invention allows byte enable signals to be used for subsequent data transfer requests prior to the completion of the initial data transfer, which reduces power consumption and allows for pipelining of data transfer requests.

    摘要翻译： 公开了一种方法，计算机系统和一组信号，允许通过总线在使用单个传送请求的主机和从机之间进行数据传输的通信，而不管传送大小和对准。 本发明提供了三个传送限定符信号，包括：包括数据传送的起始字节地址的第一信号; 第二信号，包括数据传输数据的大小; 以及第三信号，包括在数据传输的最后数据跳动期间所需的每个字节的字节使能。 本发明可用于单节拍或多节拍，对齐或未对齐的数据传送。 三个传输限定符信号的使用为从机提供了在传输开始时传输的数据跳数以及起始和结束数据跳数的对齐。 因此，从机不需要计算它将传输的字节数。 在多节拍传输方面，减少了数据传输请求的数量，从而减少了切换量，总线仲裁和所需的功耗。 此外，本发明允许在完成初始数据传输之前将字节使能信号用于随后的数据传输请求，这降低了功耗并且允许数据传送请求的流水线化。

    Reducing latency of a snoop tenure
    7.
    发明授权
    Reducing latency of a snoop tenure 失效
    减少窥探权限的延迟

    公开(公告)号：US06976132B2

    公开(公告)日：2005-12-13

    申请号：US10249304

    申请日：2003-03-28

    申请人： James N. Dieffenderfer ,  Bernard C. Drerup ,  Jaya P. Ganasan ,  Richard G. Hofmann ,  Thomas A. Sartorius ,  Thomas P. Speier ,  Barry J. Wolford

    发明人： James N. Dieffenderfer ,  Bernard C. Drerup ,  Jaya P. Ganasan ,  Richard G. Hofmann ,  Thomas A. Sartorius ,  Thomas P. Speier ,  Barry J. Wolford

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0831

    摘要： A method and system for reducing latency of a snoop tenure. A bus macro may receive a snoopable transfer request. The bus macro may determine which snoop controllers in a system will participate in the snoop transaction. The bus macro may then identify which participating snoop controllers are passive. Passive snoop controllers are snoop controllers associated with cache memories with cache lines only in the shared or invalid states of the MESI protocol. The snoop request may then be completed by the bus macro without waiting to receive responses from the passive participating snoop controllers. By not waiting for responses from passive snoop controllers, the bus macro may be able to complete the snoop request in a shorter amount of time thereby reducing the latency of the snoop tenure and improving performance of the system bus.

    摘要翻译： 一种减少窥探权限延迟的方法和系统。 总线宏可以接收可窥探的传输请求。 总线宏可以确定系统中哪个侦听控制器将参与侦听事务。 总线宏可能会识别哪些参与侦听控制器是被动的。 被动侦听控制器是与高速缓存存储器相关联的监听控制器，其高速缓存线仅在MESI协议的共享或无效状态。 然后可以由总线宏完成窥探请求，而不等待从被动参与侦听控制器接收响应。 通过不等待来自被动侦听控制器的响应，总线宏可能能够在更短的时间内完成窥探请求，从而减少了窥探任务的延迟并提高了系统总线的性能。

    Bridge for interfacing buses in computer system with a direct memory access controller having dynamically configurable direct memory access channels
    8.
    发明授权
    Bridge for interfacing buses in computer system with a direct memory access controller having dynamically configurable direct memory access channels 失效
    用于在计算机系统中与具有可动态配置的直接存储器访问通道的直接存储器访问控制器接口的桥

    公开(公告)号：US5561820A

    公开(公告)日：1996-10-01

    申请号：US351220

    申请日：1994-11-30

    申请人： Patrick M. Bland ,  Daniel R. Cronin, III ,  Richard G. Hofmann ,  Dennis Moeller ,  Lance M. Venarchick

    发明人： Patrick M. Bland ,  Daniel R. Cronin, III ,  Richard G. Hofmann ,  Dennis Moeller ,  Lance M. Venarchick

    IPC分类号： G06F13/28 ,  G06F13/40

    CPC分类号： G06F13/28 ,  G06F13/4027

    摘要： A bridge interface for buses in a computer system has a direct memory access (DMA) controller that controls memory transfers in the computer system. The DMA controller has a pair of cascaded DMA controller chips that provide a plurality of DMA channels. A multiplexer circuit receives memory address signals from the DMA controller chips. The memory address signals are received in both a shifted form and an unshifted form at the multiplexer inputs. By selection of the shifted or the unshifted memory address at the multiplexer, either even or odd addresses are produced at the multiplexer output for each DMA channel, thereby selectively providing 8-bit or 16-bit memory accesses. The control of the multiplexer is programmable for each DMA channel, providing dynamic configuration of the DHA channels as either 8-bit or 16-bit channels.

    摘要翻译： 用于计算机系统中总线的桥接口具有控制计算机系统中的存储器传输的直接存储器访问（DMA）控制器。 DMA控制器具有一对提供多个DMA通道的级联DMA控制器芯片。 多路复用器电路从DMA控制器芯片接收存储器地址信号。 存储器地址信号在多路复用器输入端以移位形式和非移相形式被接收。 通过选择多路复用器处的移位或未移位的存储器地址，在多路复用器输出处产生偶数或奇数地址，用于每个DMA通道，由此选择性地提供8位或16位存储器访问。 多路复用器的控制可针对每个DMA通道进行编程，提供DHA通道作为8位或16位通道的动态配置。

    Using field programmable gate array (FPGA) technology with a microprocessor for reconfigurable, instruction level hardware acceleration
    9.
    发明授权
    Using field programmable gate array (FPGA) technology with a microprocessor for reconfigurable, instruction level hardware acceleration 有权
    使用现场可编程门阵列（FPGA）技术与微处理器进行可重配置，指令级硬件加速

    公开(公告)号：US07603540B2

    公开(公告)日：2009-10-13

    申请号：US12167202

    申请日：2008-07-02

    申请人： Andreas C. Doering ,  Silvio Dragone ,  Andreas Herkersdorf ,  Richard G. Hofmann ,  Charles E. Kuhlmann

    发明人： Andreas C. Doering ,  Silvio Dragone ,  Andreas Herkersdorf ,  Richard G. Hofmann ,  Charles E. Kuhlmann

    IPC分类号： G06F9/00 ,  G06F15/00

    CPC分类号： G06F9/3877 ,  G06F9/30181 ,  G06F9/3897 ,  G06F15/7867

    摘要： A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.

    摘要翻译： 一种用于在协处理器中动态编程现场可编程门阵列（FPGA）的方法，所述协处理器耦合到处理器，所述协处理器包括：由处理器开始执行应用程序; 从所述处理器接收到所述协处理器的指令以执行所述应用的功能; 确定协处理器中的FPGA不是用该功能的逻辑编程的; 获取功能的配置位流; 并使用配置位流对FPGA进行编程。 以这种方式，FPGA可以“即时”编程，即在执行应用期间动态地编程。 应用程序可以更频繁地利用FPGA提供的硬件加速和资源共享优势。 还提供了包括协处理器和处理器的芯片上的逻辑灵活性和空间节省。

    System for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration
    10.
    发明授权
    System for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration 有权
    使用FPGA技术与微处理器进行可重配置，指令级硬件加速的系统

    公开(公告)号：US07584345B2

    公开(公告)日：2009-09-01

    申请号：US10696865

    申请日：2003-10-30

    申请人： Andreas C. Doering ,  Silvio Dragone ,  Andreas Herkersdorf ,  Richard G. Hofmann ,  Charles E. Kuhlmann

    发明人： Andreas C. Doering ,  Silvio Dragone ,  Andreas Herkersdorf ,  Richard G. Hofmann ,  Charles E. Kuhlmann

    IPC分类号： G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

    CPC分类号： G06F9/3877 ,  G06F9/30181 ,  G06F9/3897 ,  G06F15/7867

    摘要： A method for dynamically programming Field Programmable Gate Arrays (FPGA in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising thecoprocessor and processor are provided as well.

    摘要翻译： 一种用于动态编程现场可编程门阵列的方法（协处理器中的FPGA，耦合到处理器的协处理器）包括：由处理器开始执行应用程序;从处理器接收指令到协处理器以执行应用程序的功能 ;确定协处理器中的FPGA没有用该功能的逻辑编程;获取功能的配置位流;以及使用配置位流编程FPGA，以这种方式，FPGA可以“即时”编程， 即在应用程序的执行过程中动态执行，由FPGA提供的硬件加速和资源共享优势可以被应用程序更频繁地利用，同时提供了包括微处理器和处理器在内的芯片的逻辑灵活性和空间节省。