公开(公告)号：US5389836A

公开(公告)日：1995-02-14

申请号：US72276

申请日：1993-06-04

申请人： Allan R. Bertolet ,  Albert M. Chu ,  William R. Griffin ,  John G. Petrovick, Jr. ,  Larry Wissel

发明人： Allan R. Bertolet ,  Albert M. Chu ,  William R. Griffin ,  John G. Petrovick, Jr. ,  Larry Wissel

IPC分类号： H03K19/0944 ,  H03K19/173 ,  H03K19/096 ,  H03K19/017 ,  H03K19/20

CPC分类号： H03K19/09448 ,  H03K19/1738

摘要： Cascode voltage switch (CVS) logic circuits include a CMOS logic tree having multiple logic branches and a bipolar, branch isolation transistor. Each logic branch of the logic tree changes state between a logic "1" and a logic "0", with a state change being manifested as a charging or discharging of the logic branch. The bipolar transistor comprises a multiple-emitter bipolar transistor wherein each emitter is electrically coupled to a different logic branch of the CMOS logic tree. A precharge circuit, coupled to the logic tree via the bipolar transistor, provides charge to an output of the CVS circuit prior to operation of said logic tree. The logic branches of the logic tree are charged and discharged substantially independently of one another thereby enhancing speed of the combinatorial logic circuit. Various circuit modifications and generalizations are also discussed.

摘要翻译： 串联电压开关（CVS）逻辑电路包括具有多个逻辑支路的CMOS逻辑树和双极型支路隔离晶体管。 逻辑树的每个逻辑分支在逻辑“1”和逻辑“0”之间改变状态，状态变化表现为逻辑分支的充电或放电。 双极晶体管包括多发射极双极晶体管，其中每个发射极电耦合到CMOS逻辑树的不同逻辑分支。 通过双极晶体管耦合到逻辑树的预充电电路在所述逻辑树的操作之前向CVS电路的输出提供电荷。 逻辑树的逻辑分支基本上彼此独立地充电和放电，从而提高组合逻辑电路的速度。 还讨论了各种电路修改和概括。

公开(公告)号：US4878209A

公开(公告)日：1989-10-31

申请号：US169544

申请日：1988-03-17

申请人： Robert W. Bassett ,  William R. Griffin ,  Susan A. Murphy ,  John G. Petrovick, Jr. ,  James R. Varner ,  Dennis R. Whittaker

发明人： Robert W. Bassett ,  William R. Griffin ,  Susan A. Murphy ,  John G. Petrovick, Jr. ,  James R. Varner ,  Dennis R. Whittaker

IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/30 ,  G01R31/317 ,  G11C29/50

CPC分类号： G11C29/028 ,  G01R31/3016 ,  G11C29/50 ,  G11C29/50012 ,  G11C17/14

摘要： An apparatus and method for testing an access time of a macro embedded in a LSI chip. The apparatus includes a logical gate connected to the output latches of the macro, thereby controlling the access time of the macro, and a test latch for determining an on-chip delay time between a test signal for enabling the output latches and an input signal for enabling the macro. The method includes the steps of determining the on-chip delay time between the test signal and the input signal, thereby allowing the test signal to be synchronized with the input signal, supplying the synchronized test signal to the output latches for a manufacturer specified macro access time, and testing the latched output data from the macro.

公开(公告)号：US5173906A

公开(公告)日：1992-12-22

申请号：US576646

申请日：1990-08-31

申请人： Jeffrey H. Dreibelbis ,  Erik L. Hedberg ,  John G. Petrovick, Jr.

发明人： Jeffrey H. Dreibelbis ,  Erik L. Hedberg ,  John G. Petrovick, Jr.

IPC分类号： G01R31/28 ,  G06F11/22 ,  G06F11/27 ,  G06F15/78 ,  G11C29/10 ,  G11C29/12 ,  G11C29/16 ,  G11C29/38 ,  G11C29/44 ,  H01L27/10

CPC分类号： G11C29/16 ,  G06F11/27 ,  G11C29/44 ,  G11C29/10 ,  G11C29/38

摘要： A built-in, i.e., on-chip, self-test system for a VLSI logic or memory module. A deterministic data pattern generator is provided on the VLSI chip, and operates to test a chip module and provide a fail/no-fail result, along with data identifying where the fail occurred. This location data is captured and made available for subsequent utilization. The built-in test circuitry is programmable, and is provided with a looping capability to provide enhanced burn-in testing, for example.

公开(公告)号：US4975599A

公开(公告)日：1990-12-04

申请号：US385629

申请日：1989-07-26

申请人： John G. Petrovick, Jr. ,  Robert S. Taylor

发明人： John G. Petrovick, Jr. ,  Robert S. Taylor

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H03K17/14 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0948

CPC分类号： H03K17/6872 ,  H03K17/145 ,  H03K19/00384

摘要： According to the present invention, an improved CMOS integrated circuit and an improved method of forming the circuit is provided. The circuit has a first FET device and a second FET device, and at least one performance characteristic of said first and second FET devices varies in the same manner with the variation of at least one performance related process variable condition. Each of said FET devices has an output signal at least one characteristic of which is changed by a change in the performance related variable condition. The first and second FET devices are connected such that the one output characteristic of the second FET device acts in opposition to the one output characteristic of the first FET device to provide a merged output signal representative of the combined effect of the two FET devices. The second FET device is constructed so as to be more responsive to the variations in said performance related variable condition than the first FET device and to have a weaker output signal than the first FET device, whereby the merged output signal of the two FET devices is maintained relatively constant irrespective of variations in the performance related variable condition.