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1.发明授权System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technology 失效通过液晶半导体技术中的阈值电压偏移进行交流性能调谐的系统和方法公开(公告)号：US06487701B1
公开(公告)日：2002-11-26
申请号：US09711744
申请日：2000-11-13
IPC分类号： G06F1750
CPC分类号： G01R31/3163 , G01R31/2891
摘要： A system and method are described for separating the bulk connections for FETs on a semiconductor wafer from the supply rails, testing the wafer to determine if a shift in the threshold voltage, VT, of certain devices within the wafer, as defined by the bulk-wells, can remove an AC defect in the IC circuit, and tailoring the voltage or voltages applied to the bulk nodes, post-manufacture, such that the integrated circuit meets its performance targets or is sorted to a more valuable performance level. The method requires generating a gate level netlist of the IC's circuitry and performing timing calculations on these circuit netlists using static timing analyses, functional delay simulations, circuit activity analyses, and functional performance testing. The failures are then correlated to respective IC circuits, worst case slack circuits are investigated, and proposed changes to the threshold voltages are employed in the hardware.
摘要翻译： 描述了一种系统和方法，用于将半导体晶片上的FET的体连接与电源轨分开，测试晶片以确定晶片内的某些器件的阈值电压VT是否偏移， 孔可以去除IC电路中的AC缺陷，并且定制施加到散装节点的电压或电压，后制造，使得集成电路满足其性能目标或被分类到更有价值的性能水平。 该方法需要生成IC电路的门级网表，并使用静态时序分析，功能延迟模拟，电路活动分析和功能性能测试来对这些电路网表执行定时计算。 然后将故障与相应的IC电路相关联，最坏情况下调查松弛电路，并且在硬件中采用提出的阈值电压的改变。
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2.发明授权Asynchronous packet based dual port link list header and data credit management structure 有权基于异步数据包的双端口链路列表头和数据信用管理结构公开(公告)号：US07752355B2
公开(公告)日：2010-07-06
申请号：US10832658
申请日：2004-04-27
IPC分类号： G06F5/00
CPC分类号： G06F13/4059
摘要： An asynchronous data transfer interface is provided across a boundary that allows high bandwidth data transfers which are packet based as defined by PCI_Express architecture, and has general utility in processor-based applications like servers, desktop applications, and mobile applications. A shared set of multi-port RAM buffers allow both an application layer AL and a transaction layer TL access to a communication protocol layer in a defined process that allows both the application layer AL and the transaction layer TL to read and manage the buffers in a 16 byte boundary in a manner that allows a data credit to be decoupled from a header credit.
摘要翻译： 跨越边界提供异步数据传输接口，允许高速带宽数据传输，这些数据传输是由PCI_Express架构定义的基于分组的，并且在基于处理器的应用程序（如服务器，桌面应用程序和移动应用程序）中具有通用功能。 共享的一组多端口RAM缓冲器允许应用层AL和事务层TL在定义的过程中访问通信协议层，允许应用层AL和事务层TL两者读取和管理缓冲区中的缓冲区 16字节边界以允许从标题信用中分离数据信用的方式。
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公开(公告)号：US06978234B1
公开(公告)日：2005-12-20
申请号：US09602369
申请日：2000-06-23
CPC分类号： G06F11/261
摘要： A method of creating a prototype data processing system, by configuring a hardware development chip (HDC) according to user-defined settings, building user-defined logic adapted to function with the configured development chip, and allowing for the re-configuration of the HDC and user-defined logic after debugging. The HDC has several data processing macros including a processor core macro, a ROM emulation macro, a memory macro, and a bus macro. The macros may be configured by a configuration pin block which is connected to external configuration pins on the HDC. Customer logic is built using a field programmable gate array, which is interconnected with external ports of the HDC. The HDC and customer logic are verified using a debug port on the HDC, which is connected to a debug workstation. The invention allows a user to easily and quickly debug an application-specific integrated circuit (ASIC) design with a unique version of selected processor cores.
摘要翻译： 一种创建原型数据处理系统的方法，通过根据用户定义的设置配置硬件开发芯片（HDC），构建适用于配置的开发芯片的用户定义逻辑，并允许重新配置HDC 和调试后的用户定义逻辑。 HDC具有多个数据处理宏，包括处理器核心宏，ROM仿真宏，存储器宏和总线宏。 宏可以由连接到HDC上的外部配置引脚的配置引脚块来配置。 客户逻辑使用与HDC的外部端口互连的现场可编程门阵列构建。 HDC和客户逻辑使用HDC上的调试端口进行验证，该调试端口连接到调试工作站。 本发明允许用户使用所选择的处理器核心的唯一版本容易且快速地调试专用集成电路（ASIC）设计。
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公开(公告)号：US5784595A
公开(公告)日：1998-07-21
申请号：US908214
申请日：1997-08-07
申请人： Robert J. Devins , Stephen Hon , Patrick Kam , Emory D. Keller
发明人： Robert J. Devins , Stephen Hon , Patrick Kam , Emory D. Keller
CPC分类号： G06F9/45537 , G06F13/105 , G06F13/28
摘要： A method and system are disclosed for simulating a direct memory access (DMA) function to access memory in a host computer having a DMA controller for the purpose of enabling the transfer of data between the host memory and a computer accessory data handling device not capable of DMA operation. The accessory data handling device can be operably connected to the host. The address contents of the DMA controller can be read to determine the location in the host memory where data is to be transferred from the host memory to the accessory data handling device or from the accessory data handling device to the host memory. Data is read from the host memory at the address specified in the DMA controller and written to the accessory data handling device or read from the accessory data handling device and written to the host memory at the address specified by the DMA controller, respectively. The host computer is informed that a DMA operation corresponding to the data transfer has been completed when the data transfer required has been completed.
摘要翻译： 公开了一种用于模拟直接存储器访问（DMA）功能以访问具有DMA控制器的主计算机中的存储器的方法和系统，以便能够在主机存储器和不能够执行以下操作的计算机辅助数据处理设备之间传输数据 DMA操作。 附件数据处理装置可以可操作地连接到主机。 可以读取DMA控制器的地址内容，以确定主机存储器中要从主机存储器传输到附件数据处理设备或从附件数据处理设备传输到主机存储器的位置。 数据从DMA控制器中指定的地址从主机存储器读取，并写入附件数据处理设备或从附件数据处理设备读取，并分别以DMA控制器指定的地址写入主机存储器。 当完成数据传输时，主计算机通知对应于数据传输的DMA操作已经完成。
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5.发明授权Structure for system for and method of performing high speed memory diagnostics via built-in-self-test 失效用于通过内置自检进行高速存储器诊断的系统和方法的结构公开(公告)号：US07870454B2
公开(公告)日：2011-01-11
申请号：US12126452
申请日：2008-05-23
CPC分类号： G11C29/40 , G01R31/31703 , G01R31/31704 , G11C2029/3202
摘要： A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
摘要翻译： 公开了一种用于通过内置自检（BIST）执行高速存储器诊断的系统和方法的设计结构。 特别地，测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。 测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。 通过BIST执行高速存储器诊断的方法包括但不限于预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑的等待时间的值，设置BIST周期计数器 将可变延迟预置为零，重新执行测试算法并执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。
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6.发明授权System and method for performing high speed memory diagnostics via built-in-self-test 有权通过内置自检进行高速存储器诊断的系统和方法公开(公告)号：US07607060B2
公开(公告)日：2009-10-20
申请号：US11531035
申请日：2006-09-12
CPC分类号： G11C29/44 , G11C2029/3202
摘要： A system and method for performing high speed memory diagnostics via built-in-self-test (BIST). A test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method includes presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm, performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
摘要翻译： 一种用于通过内置自检（BIST）执行高速存储器诊断的系统和方法。 测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。 测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。 一种方法包括预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑等待时间的值，将BIST周期计数器设置为递减模式，将可变延迟预置为零，重新执行 测试算法，执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。
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7.发明授权Automatic shutdown or throttling of a bist state machine using thermal feedback 失效使用热反馈自动关闭或调节双速状态机公开(公告)号：US07458000B2
公开(公告)日：2008-11-25
申请号：US11278238
申请日：2006-03-31
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C2029/5002
摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.
摘要翻译： 内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关的BIST测试操作。 热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。 响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。 这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。
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8.发明申请SYSTEM FOR AND METHOD OF PERFORMING HIGH SPEED MEMORY DIAGNOSTICS VIA BUILT-IN-SELF-TEST 有权通过内置自检来执行高速记忆诊断的系统和方法公开(公告)号：US20080082883A1
公开(公告)日：2008-04-03
申请号：US11531035
申请日：2006-09-12
IPC分类号： G01R31/28
CPC分类号： G11C29/44 , G11C2029/3202
摘要： A system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
摘要翻译： 公开了一种通过内置自检（BIST）执行高速存储器诊断的系统和方法。 特别地，测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。 测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。 通过BIST执行高速存储器诊断的方法包括但不限于预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑的等待时间的值，设置BIST周期计数器 将可变延迟预置为零，重新执行测试算法并执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。
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9.发明授权Audio adapter card and method for trapping audio command and producing sound corresponding to the trapped command 失效用于捕获音频命令并产生与被捕获命令对应的声音的音频适配器卡和方法
公开(公告)号：US5768631A
公开(公告)日：1998-06-16
申请号：US533487
申请日：1995-09-25
申请人： Patrick K. Kam , Robert J. Devins , Stephen Hon , Emory D. Keller
发明人： Patrick K. Kam , Robert J. Devins , Stephen Hon , Emory D. Keller
摘要： An audio system is provided for generating audio sound for a host computer. It includes an interface connector for connection with the host computer; an interface controller for communicating with the host computer using the interface connector; a trap adapted to trap audio instruction signals from an application running on the host, such as a game having an audio portion; a trap controller adapted to control the trap; and an audio output. The system operates with an interface communicator which is adapted to respond to a request from the interface controller to read information from the trap and send audio output instruction to the audio output to generate audio sound.
摘要翻译： 提供音频系统以产生用于主计算机的音频声音。 它包括用于与主机连接的接口连接器; 接口控制器，用于使用接口连接器与主机通信; 陷阱，适于从主机上运行的应用捕获音频指令信号，例如具有音频部分的游戏; 适于控制所述陷阱的陷阱控制器; 和音频输出。 该系统与接口通信器一起操作，该接口通信器适于响应来自接口控制器的请求以从陷阱读取信息，并将音频输出指令发送到音频输出以产生音频声音。
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公开(公告)号：US07735031B2
公开(公告)日：2010-06-08
申请号：US11841125
申请日：2007-08-20
申请人： Valerie Hornbeck Chickanosky , Kevin William Gorman , Emory D. Keller , Michael Richard Ouellette
发明人： Valerie Hornbeck Chickanosky , Kevin William Gorman , Emory D. Keller , Michael Richard Ouellette
IPC分类号： G06F17/50
CPC分类号： G01R31/31724 , G01R31/31721
摘要： A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.
摘要翻译： 一种包括用于启用枚举操作的控制器的系统。 枚举操作由系统中的控制器（110）和逻辑元件（120）执行，使得系统中的每个逻辑元件分配自身唯一的标识符。 然后，每个逻辑元件可以被另一个源控制，或者具有与系统中的其它逻辑元件通信的手段。 独特的标识符可以实现更大的系统灵活性，从而降低成本并提高效率。
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