公开(公告)号：US06487701B1

公开(公告)日：2002-11-26

申请号：US09711744

申请日：2000-11-13

申请人： Alvar A. Dean ,  Jerry D. Hayes ,  Joseph A. Iadanza ,  Emory D. Keller ,  Sebastian T. Ventrone

发明人： Alvar A. Dean ,  Jerry D. Hayes ,  Joseph A. Iadanza ,  Emory D. Keller ,  Sebastian T. Ventrone

IPC分类号： G06F1750

CPC分类号： G01R31/3163 ,  G01R31/2891

摘要： A system and method are described for separating the bulk connections for FETs on a semiconductor wafer from the supply rails, testing the wafer to determine if a shift in the threshold voltage, VT, of certain devices within the wafer, as defined by the bulk-wells, can remove an AC defect in the IC circuit, and tailoring the voltage or voltages applied to the bulk nodes, post-manufacture, such that the integrated circuit meets its performance targets or is sorted to a more valuable performance level. The method requires generating a gate level netlist of the IC's circuitry and performing timing calculations on these circuit netlists using static timing analyses, functional delay simulations, circuit activity analyses, and functional performance testing. The failures are then correlated to respective IC circuits, worst case slack circuits are investigated, and proposed changes to the threshold voltages are employed in the hardware.

摘要翻译： 描述了一种系统和方法，用于将半导体晶片上的FET的体连接与电源轨分开，测试晶片以确定晶片内的某些器件的阈值电压VT是否偏移， 孔可以去除IC电路中的AC缺陷，并且定制施加到散装节点的电压或电压，后制造，使得集成电路满足其性能目标或被分类到更有价值的性能水平。 该方法需要生成IC电路的门级网表，并使用静态时序分析，功能延迟模拟，电路活动分析和功能性能测试来对这些电路网表执行定时计算。 然后将故障与相应的IC电路相关联，最坏情况下调查松弛电路，并且在硬件中采用提出的阈值电压的改变。

公开(公告)号：US08862426B2

公开(公告)日：2014-10-14

申请号：US11961442

申请日：2007-12-20

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Sani R. Nassif

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Sani R. Nassif

IPC分类号： G01R19/00 ,  G01R31/00 ,  G01R31/14 ,  G01R31/28 ,  G01R31/3185

CPC分类号： G01R31/2884 ,  G01R31/2831 ,  G01R31/318533 ,  G01R31/318558

摘要： A method and test system for fast determination of parameter variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment. A test array having individually selectable devices is stimulated under computer control to select each of the devices sequentially. A test output from the array provides a current or voltage that dependent on a particular device parameter. The sequential selection of the devices produces a voltage or current waveform, characteristics of which are measured using a digital multi-meter that is interfaced to the computer. The rms value of the current or voltage at the test output is an indication of the standard deviation of the parameter variation and the DC value of the current or voltage is an indication of the mean value of the parameter.

摘要翻译： 用于快速确定参数变化统计的方法和测试系统提供了使用低计算能力和容易获得的测试设备来确定过程变化和参数统计的机制。 在计算机控制下刺激具有可单独选择的装置的测试阵列以依次选择每个装置。 阵列的测试输出提供依赖于特定器件参数的电流或电压。 器件的顺序选择产生电压或电流波形，其特性使用与计算机连接的数字万用表进行测量。 测试输出端的电流或电压的有效值表示参数变化的标准偏差，电流或电压的直流值表示参数的平均值。

公开(公告)号：US20120262187A1

公开(公告)日：2012-10-18

申请号：US13524208

申请日：2012-06-15

申请人： Fadi H. Gebara ,  Jerry D. Hayes ,  John P. Keane ,  Sani R. Nassif ,  Jeremy D. Schaub

发明人： Fadi H. Gebara ,  Jerry D. Hayes ,  John P. Keane ,  Sani R. Nassif ,  Jeremy D. Schaub

IPC分类号： G01R27/28

CPC分类号： G01R31/31725 ,  G01R31/2856

摘要： A method and test circuit provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.

摘要翻译： 一种方法和测试电路提供测量，以准确表征由于负偏压温度不稳定性（NBTI）和正偏压温度不稳定性（PBTI）引起的阈值电压变化。 可以研究由于应力应用的快速重复引起的偏置温度不稳定性恢复曲线和/或偏置温度偏移。 为了提供精确的测量，当应力以几十纳秒的间隔施加，同时避免不必要的恢复时，和/或实现纳秒范围内的恢复曲线采样分辨率，使用延迟进行多个延迟或环形振荡器频率测量 由具有实质上仅由NBTI或PBTI效应引起的延迟变化的延迟元件形成的线。 延迟元件中的器件受到应力，然后延迟线/环形振荡器被操作以测量一个或多个量级的纳秒的一个或多个测量周期的阈值电压变化。

公开(公告)号：US08217671B2

公开(公告)日：2012-07-10

申请号：US12492619

申请日：2009-06-26

申请人： Kanak B. Agarwal ,  Peter A. Habitz ,  Jerry D. Hayes ,  Ying Liu ,  Deborah M. Massey ,  Alvin W. Strong

发明人： Kanak B. Agarwal ,  Peter A. Habitz ,  Jerry D. Hayes ,  Ying Liu ,  Deborah M. Massey ,  Alvin W. Strong

IPC分类号： G01R31/00

CPC分类号： G01R31/2858

摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.

摘要翻译： 提供了一种用于恒流电迁移应力测试的并行阵列架构。 并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。 该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。 此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分 电流源逻辑。 使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。

公开(公告)号：US07868640B2

公开(公告)日：2011-01-11

申请号：US12061077

申请日：2008-04-02

申请人： Kanak B Agarwal ,  Nazmul Habib ,  Jerry D. Hayes ,  John Greg Massey ,  Alvin W. Strong

发明人： Kanak B Agarwal ,  Nazmul Habib ,  Jerry D. Hayes ,  John Greg Massey ,  Alvin W. Strong

IPC分类号： G01R31/26

CPC分类号： G01R31/2621 ,  G01R31/3004

摘要： A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.

摘要翻译： 一种方法和测试电路提供测量以帮助理解时变阈值电压变化，例如负偏压温度不稳定性和正偏压温度不稳定性。 为了在阈值变化的早期阶段提供精确的测量，电流产生电路与被测器件集成在衬底上，其可以是从器件阵列中选择的器件。 电流产生电路可以是响应于由测试系统提供的外部供应电流的电流镜。 可以包括电压源电路以保持晶体管的漏 - 源电压恒定，尽管不是必需的。 在测量阶段之前施加应力，其可以包括在应力消除之后的可控松弛周期。

公开(公告)号：US20080284460A1

公开(公告)日：2008-11-20

申请号：US12141862

申请日：2008-06-18

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/36

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

摘要翻译： 使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。 这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。 通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。 然后通过将表示线性关系的线的斜率除以激励电压来导出电容。 可以对不同的电子设备进行测试，包括晶体管和互连结构。

公开(公告)号：US07418689B2

公开(公告)日：2008-08-26

申请号：US10908102

申请日：2005-04-27

申请人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

发明人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

摘要翻译： 电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。 布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间 信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且 在第一布线路径和第二布线路径横越的各布线层内。 此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

公开(公告)号：US07174523B2

公开(公告)日：2007-02-06

申请号：US10710734

申请日：2004-07-30

申请人： James J. Engel ,  Jerry D. Hayes

发明人： James J. Engel ,  Jerry D. Hayes

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5045

摘要： The invention presents a method of accommodating for across chip line variation (ACLV) and/or changing static timing of an integrated circuit design. The invention first establishes a circuit design having initial timing requirements and an initial voltage supply and also establishes a relationship between gate timing variations caused by voltage supply changes and gate timing variations caused by manufacturing processing changes. Then, according to the customer's orders that change the initial timing requirements to revised timing requirements, the invention changes the initial voltage supply to a revised voltage supply to accommodate the revised timing requirements (and ACLV if desired) based on the relationship between voltage limits and transistor delay. This process of changing the initial voltage supply does not alter the circuit design.

摘要翻译： 本发明提出了一种适应跨芯片线路变化（ACLV）和/或改变集成电路设计的静态定时的方法。 本发明首先建立了具有初始定时要求和初始电压供应的电路设计，并且还建立由电压供应变化引起的门定时变化与由制造处理变化引起的门时序变化之间的关系。 然后，根据客户的订单，将初始时间要求改变为修订的时序要求，本发明将初始电压供应改变为修正的电源，以适应修订的时序要求（如果需要，则根据需要进行ACLV），基于电压限制和 晶体管延迟。 改变初始电压源的这个过程不会改变电路设计。

公开(公告)号：US08229683B2

公开(公告)日：2012-07-24

申请号：US12962726

申请日：2010-12-08

申请人： Fadi H. Gebara ,  Jerry D. Hayes ,  John P. Keane ,  Sani R. Nassif ,  Jeremy D. Schaub

发明人： Fadi H. Gebara ,  Jerry D. Hayes ,  John P. Keane ,  Sani R. Nassif ,  Jeremy D. Schaub

IPC分类号： G01L1/00

CPC分类号： G01R31/31725 ,  G01R31/2856

摘要： A method, test circuit and test system provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.

摘要翻译： 一种方法，测试电路和测试系统提供测量以精确表征由于负偏压温度不稳定性（NBTI）和正偏压温度不稳定性（PBTI）引起的阈值电压变化。 可以研究由于应力应用的快速重复引起的偏置温度不稳定性恢复曲线和/或偏置温度偏移。 为了提供精确的测量，当应力以几十纳秒的间隔施加，同时避免不必要的恢复时，和/或实现纳秒范围内的恢复曲线采样分辨率，使用延迟进行多个延迟或环形振荡器频率测量 由具有实质上仅由NBTI或PBTI效应引起的延迟变化的延迟元件形成的线。 延迟元件中的器件受到应力，然后延迟线/环形振荡器被操作以测量一个或多个量级的纳秒的一个或多个测量周期的阈值电压变化。

公开(公告)号：US08154309B2

公开(公告)日：2012-04-10

申请号：US12489656

申请日：2009-06-23

申请人： Kanak B. Agarwal ,  Jerry D. Hayes

发明人： Kanak B. Agarwal ,  Jerry D. Hayes

IPC分类号： G01R27/26

CPC分类号： G01R31/27 ,  G01R31/2853

摘要： A configurable PSRO measurement circuit is used to measure the frequency dependent capacitance of a target through silicon via (TSV) or other conductive structure. Measurements of the target structure are aided by using adjustable resistors and a de-embedding structure to measure the effects of parasitic capacitance, CPAR. Current is measured to both the device under test (DUT) and the de-embedding structure. From these measurements, the frequency dependent capacitance of the DUT is calculated.

摘要翻译： 可配置的PSRO测量电路用于通过硅通孔（TSV）或其他导电结构测量目标的频率相关电容。 通过使用可调电阻和去嵌入结构来测量目标结构的测量来测量寄生电容CPAR的影响。 电流被测量到被测器件（DUT）和去嵌入结构。 从这些测量中，计算DUT的频率相关电容。