公开(公告)号：US11720444B1

公开(公告)日：2023-08-08

申请号：US17548190

申请日：2021-12-10

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Osnat Katz ,  Nir Bar-Or ,  Adi Habusha

IPC: G06F11/07 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0891

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0772 ,  G06F12/0238 ,  G06F12/0891

Abstract: A system captures errors and stores an obsolete line bit qualifier per cache entry that can be used to dynamically mark a specific cache entry as obsolete. For example, the cache entry can be marked as obsolete after detecting repetitive single-bit errors on a same cache entry within a predetermined period of time. For cache lines marked as obsolete, a cache controller can ensure that the cache line entry remains unused. The detection of a repetitive single-bit error can be accomplished by implementing a counter per cache entry and a timer. The counter counts errors within a timer window, and a repetitive error is reported if the counter reaches a threshold level. By catching repetitive single-bit errors before such errors spread to multi-bit errors, the system can increase the life span of the server computer.

公开(公告)号：US11343176B2

公开(公告)日：2022-05-24

申请号：US16450837

申请日：2019-06-24

Applicant: Amazon Technologies, Inc.

Inventor： Sergey Kleyman ,  Adi Habusha ,  Lior Podorowski ,  Ofer Naaman

IPC: H04L12/00 ,  H04L45/302 ,  H04L45/745 ,  H04L47/24 ,  H04L67/568 ,  H04L49/20

Abstract: In various implementations, provided are systems and methods for an integrated circuit including a completer device, a requester device, and an interconnect fabric. The requester device is configured to generate transactions to the completer device, where each transaction includes a request packet that includes an attribute associated with the completer device; and the interconnect fabric is coupled to the requester device and the completer device. The integrated circuit can also include a QoS regulator configured to identify, based on a first attribute associated with the completer device, a first QoS value establishing a first priority level for a first request packet generated by the requester device, and modify the first request packet to include the first QoS value.

公开(公告)号：US11275690B1

公开(公告)日：2022-03-15

申请号：US16995091

申请日：2020-08-17

Applicant: Amazon Technologies, Inc.

Inventor： Michael Zuzovski ,  Ofer Naaman ,  Adi Habusha

IPC: G06F12/084 ,  G06F12/0871 ,  G06F9/54

Abstract: Techniques are disclosed for transferring a message between a sender agent and a receiver agent via a shared memory having a main memory and a cache. Feedback data indicative of a number of read messages in the shared memory is generated by the receiver agent. The feedback data is sent from the receiver agent to the sender agent. A number of unread messages in the shared memory is estimated by the sender agent based on the number of read messages. A threshold for implementing a caching policy is set by the sender agent based on the feedback data. The message is designated as cacheable if the number of unread messages is less than the threshold and as non-cacheable if the number of unread messages is greater than the threshold. The message is written to the shared memory based on the designation.

公开(公告)号：US10863009B2

公开(公告)日：2020-12-08

申请号：US16435266

申请日：2019-06-07

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Erez Izenberg ,  Nafea Bshara

IPC: H04L29/06 ,  G06F17/30 ,  H04L12/861 ,  H04L12/931 ,  H04L12/721 ,  H04L12/741 ,  H04L12/851 ,  H04L12/801 ,  H04L1/00 ,  G06F9/30 ,  G06F13/38 ,  H04L12/803

Abstract: A system, comprising: a configurable parser that comprises one or more configurable parsing engines, wherein the configurable parser is arranged to receive a packet and to extract from the packet headers associated with a set of protocols that comprises at least one protocol; a packet type detection unit that is arranged to determine a type of the packet in response to the set of protocols; and a configurable data integrity unit that comprises a configuration unit and at least one configurable data integrity engine; wherein the configuration unit is arranged to configure the at least one configurable data integrity engine according to the set of protocols; and wherein the at least one configurable data integrity engine is arranged to perform data integrity processing of the packet to provide at least one data integrity result.

公开(公告)号：US11625353B1

公开(公告)日：2023-04-11

申请号：US17444351

申请日：2021-08-03

Applicant: Amazon Technologies, Inc.

Inventor： Itamar Bonne ,  Simaan Bahouth ,  Ofer Naaman

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42

Abstract: Techniques to prioritize serially transmitted data are described. The sequence of serial data segments being transmitted across a communication interface is modified such that prioritized segments that may require a higher refresh rate are transmitted more frequently than regular data segments. A prioritization configuration register can be implemented in both the transmitter and the receiver such that both sides are programmed with the altered sequence of transmission. The prioritization configuration stored in the prioritization configuration register can indicate the points in the sequence where the out-of-order transmission occurs, and which data segments are transmitted in them. The transmitter can use this information to serialize the data segments according to the prioritization, and the receiver can re-parallelize the received data as indicated by the altered sequence.

公开(公告)号：US11042494B1

公开(公告)日：2021-06-22

申请号：US16014833

申请日：2018-06-21

Applicant: Amazon Technologies, inc.

Inventor： Ali Ghassan Saidi ,  Adi Habusha ,  Itai Avron ,  Tzachi Zidenberg ,  Ofer Naaman

IPC: G06F9/455 ,  G06F13/24 ,  G06F11/07

Abstract: An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

公开(公告)号：US10320956B2

公开(公告)日：2019-06-11

申请号：US14594137

申请日：2015-01-11

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Erez Izenberg ,  Nafea Bshara

IPC: G06F17/30 ,  H04L29/06 ,  H04L12/851 ,  H04L12/801 ,  H04L1/00 ,  G06F9/30 ,  G06F13/38 ,  H04L12/803

Abstract: A system, comprising: a configurable parser that comprises one or more configurable parsing engines, wherein the configurable parser is arranged to receive a packet and to extract from the packet headers associated with a set of protocols that comprises at least one protocol; a packet type detection unit that is arranged to determine a type of the packet in response to the set of protocols; and a configurable data integrity unit that comprises a configuration unit and at least one configurable data integrity engine; wherein the configuration unit is arranged to configure the at least one configurable data integrity engine according to the set of protocols; and wherein the at least one configurable data integrity engine is arranged to perform data integrity processing of the packet to provide at least one data integrity result.

公开(公告)号：US12069154B2

公开(公告)日：2024-08-20

申请号：US18316126

申请日：2023-05-11

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Erez Izenberg ,  Nafea Bshara

IPC: H04L69/22 ,  G06F16/00 ,  G06F16/13 ,  G06F16/182 ,  G06F16/245 ,  G06F16/2458 ,  G06F16/25 ,  G06F16/90 ,  G06F16/903 ,  H04L45/00 ,  H04L45/74 ,  H04L47/10 ,  H04L47/2425 ,  H04L49/60 ,  H04L49/90 ,  H04L69/00 ,  H04L69/12 ,  H04L69/16 ,  G06F9/30 ,  G06F13/38 ,  H04L1/00 ,  H04L47/125

CPC classification number: H04L69/22 ,  G06F16/00 ,  G06F16/134 ,  G06F16/182 ,  G06F16/245 ,  G06F16/2471 ,  G06F16/254 ,  G06F16/90 ,  G06F16/90344 ,  H04L45/38 ,  H04L45/74 ,  H04L47/10 ,  H04L47/2433 ,  H04L49/602 ,  H04L49/90 ,  H04L69/02 ,  H04L69/12 ,  H04L69/16 ,  G06F9/3001 ,  G06F13/385 ,  H04L1/0066 ,  H04L47/125 ,  Y02D10/00

Abstract: A packet processing technique can include receiving a packet, and parsing the packet based on a protocol field to generate a parse result vector. The parse result vector is used to select between forwarding the packet to a virtual machine executing on a host processing integrated circuit, forwarding the packet to a physical media access controller, multicasting the packet to multiple virtual machines executing on the host processing integrated circuit, and sending the packet to a hypervisor.

公开(公告)号：US11687462B1

公开(公告)日：2023-06-27

申请号：US17653612

申请日：2022-03-04

Applicant: Amazon Technologies, Inc.

Inventor： Michael Zuzovski ,  Ofer Naaman ,  Adi Habusha

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0871 ,  G06F9/54

CPC classification number: G06F12/084 ,  G06F9/544 ,  G06F12/0871

Abstract: Techniques are disclosed for transferring a message between a sender agent and a receiver agent via a shared memory having a main memory and a cache. Feedback data indicative of a number of read messages in the shared memory is generated by the receiver agent. The feedback data is sent from the receiver agent to the sender agent. A number of unread messages in the shared memory is estimated by the sender agent based on the number of read messages. A threshold for implementing a caching policy is set by the sender agent based on the feedback data. The message is designated as cacheable if the number of unread messages is less than the threshold and as non-cacheable if the number of unread messages is greater than the threshold. The message is written to the shared memory based on the designation.

公开(公告)号：US20210084128A1

公开(公告)日：2021-03-18

申请号：US17247147

申请日：2020-12-01

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Erez Izenberg ,  Nafea Bshara

IPC: H04L29/06 ,  H04L12/861 ,  H04L12/931 ,  H04L12/721 ,  H04L12/741 ,  H04L12/851 ,  H04L12/801 ,  G06F16/182 ,  G06F16/245 ,  G06F16/00 ,  G06F16/13

Abstract: A packet processing technique can include selecting a protocol field from the packet, and performing a comparison of the selected protocol field with comparison data in a compare logic array to output a protocol index. The protocol index can be used as an address to read parsing commands from a parse control table, and a parse result can be generated based on executing the parsing commands on the packet. The parse results are used to derive a parse result vector, which can be used by a forwarding engine to forward the packet.