公开(公告)号：US11138130B1

公开(公告)日：2021-10-05

申请号：US16813606

申请日：2020-03-09

Applicant: Amazon Technologies, Inc.

Inventor： Ali Ghassan Saidi

IPC: G06F12/10 ,  G06F12/1027 ,  G06F12/1009 ,  G06F9/455 ,  G06F12/0891

Abstract: A translation buffer is provided in parallel to a translation lookaside buffer (TLB) to cache translations between intermediate physical addresses (IPAs) and pointers for entries in the TLB corresponding to the IPAs. The pointers can be used to identify and invalidate only certain entries in the TLB as compared to invalidating the whole TLB.

公开(公告)号：US10884790B1

公开(公告)日：2021-01-05

申请号：US15969650

申请日：2018-05-02

Applicant: Amazon Technologies, Inc.

Inventor： Ali Ghassan Saidi ,  Adi Habusha

IPC: G06F9/455 ,  G06F9/48 ,  G06F12/1009 ,  G06F12/1081 ,  G06F3/06 ,  G06F12/1027

Abstract: Systems and methods are provided to reduce the number of redundant copy operations performed as part of a live migration of a virtual machine executing a guest. While pre-copying for the live migration of the VM, the guest may continue to write to the pages. A hypervisor may clear the dirty pages and schedule the copy operations of the modified pages in a processing engine for copying to a target device. In one embodiment, before initiating the copy operation, the processing engine may check if the page has been modified again and omit the copy operation if the page has been modified again.

公开(公告)号：US11537430B1

公开(公告)日：2022-12-27

申请号：US16783935

申请日：2020-02-06

Applicant: Amazon Technologies, Inc.

Inventor： Ali Ghassan Saidi

IPC: G06F9/48 ,  G06F9/455

Abstract: A wait optimizer circuit can be coupled to a processor to monitor an entry of a virtual CPU (vCPU) into a wait mode to acquire a ticket lock. The wait optimizer can introduce an amount of delay, while the vCPU is in the wait mode, with an assumption that the spinlock may be resolved before sending a wake up signal to the processor for rescheduling. The wait optimizer can also record a time stamp only for a first entry of the vCPU from a plurality of entries into the wait mode within a window of time. The time stamps for vCPUs contending for the same ticket lock can be used by a hypervisor executing on the processor for rescheduling the vCPUs.

公开(公告)号：US11237981B1

公开(公告)日：2022-02-01

申请号：US16588206

申请日：2019-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Ali Ghassan Saidi ,  Ohad Gdalyahu

IPC: G06F12/122 ,  G06F12/0831 ,  G06F9/455 ,  G06F13/28

Abstract: Methods and integrated circuit devices for accelerating memory page classification are provided. Memory systems typically have a combination of faster memory devices and slower memory devices. Frequently accessed memory pages (hot pages) should be maintained in the faster memory devices while less frequently accessed memory pages (cold pages) should be maintained in the slower memory devices. Classification of memory pages as hot or cold pages may be performed by an integrated circuit device that reads counter values that count transactions to corresponding memory pages. A distribution of counter values may be determined, and memory pages may be identified as hot or cold memory pages based on thresholds applied to the distribution.

公开(公告)号：US10592428B1

公开(公告)日：2020-03-17

申请号：US15717808

申请日：2017-09-27

Applicant: Amazon Technologies, Inc.

Inventor： Ali Ghassan Saidi

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/1009 ,  G06F9/455 ,  G06F12/0891

Abstract: A translation buffer is provided in parallel to a translation lookaside buffer (TLB) to cache translations between intermediate physical addresses (IPAs) and pointers for entries in the TLB corresponding to the IPAs. The pointers can be used to identify and invalidate only certain entries in the TLB as compared to invalidating the whole TLB.

公开(公告)号：US12197938B1

公开(公告)日：2025-01-14

申请号：US17643756

申请日：2021-12-10

Applicant: Amazon Technologies, Inc.

Inventor： Ali Ghassan Saidi ,  Adi Habusha

IPC: G06F9/455 ,  G06F13/16 ,  G06F13/42

Abstract: An input/output (I/O) device can initiate data migration of a virtual machine (VM) instance from a source device to a target device. The data migration of the VM instance may include migrating the data for the VM instance and tag data associated with the data. The data for the VM instance and the tag data may be stored together in a source memory. A first read request from the I/O device can enable a memory controller in the source device to read the data for the VM instance and the tag data together, store the tag data in a tag data buffer, and transmit the data for the VM instance to the target device. A second read request from the I/O device can read the stored tag data from the tag data buffer and transmit to the target device. The target device can write the data for the VM instance together with the tag data in the target memory.

公开(公告)号：US12093189B1

公开(公告)日：2024-09-17

申请号：US16588394

申请日：2019-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Ali Ghassan Saidi ,  Adi Habusha ,  Roland Paterson-Jones ,  Ohad Gdalyahu

IPC: G06F12/122

CPC classification number: G06F12/122 ,  G06F2212/1016 ,  G06F2212/304

Abstract: Methods and integrated circuit devices for recording memory-side page activity are provided. Memory systems typically have a combination of faster memory devices and slower memory devices. Frequently accessed memory pages (hot pages) should be maintained in the faster memory devices while less frequently accessed memory pages (cold pages) should be maintained in the slower memory devices. To determine the memory pages that should be moved between the faster memory devices and the slower memory devices, counters may be implemented to count transactions to the memory pages. The counter values may be periodically checked to identify memory pages that can be moved from faster memory devices to slower memory devices, and vice-versa.

公开(公告)号：US20240095367A1

公开(公告)日：2024-03-21

申请号：US17662610

申请日：2022-05-09

Applicant: Amazon Technologies, Inc.

Inventor： Said Bshara ,  Nafea Bshara ,  Ali Ghassan Saidi

IPC: G06F21/57

CPC classification number: G06F21/577 ,  G06F2221/034

Abstract: A data guard circuit can be used to verify encryption of the data traffic on a bus between two integrated circuit (IC) devices. The data guard circuit can monitor the data traffic on the bus to analyze the data traffic based on a configuration. The analysis can be performed by sampling the data traffic, and a statistical data pattern can be identified in the sampled data traffic. The statistical data pattern can be compared with a threshold to determine whether the data traffic is encrypted. The data guard circuit can generate a notification if the data traffic is not encrypted as expected so that an appropriate action can be taken to protect the data.

公开(公告)号：US11042494B1

公开(公告)日：2021-06-22

申请号：US16014833

申请日：2018-06-21

Applicant: Amazon Technologies, inc.

Inventor： Ali Ghassan Saidi ,  Adi Habusha ,  Itai Avron ,  Tzachi Zidenberg ,  Ofer Naaman

IPC: G06F9/455 ,  G06F13/24 ,  G06F11/07

Abstract: An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

公开(公告)号：US10901492B1

公开(公告)日：2021-01-26

申请号：US16369696

申请日：2019-03-29

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Ron Diamant ,  Randy Renfu Huang ,  Ali Ghassan Saidi

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/329 ,  G06F7/523 ,  G06F7/57 ,  G06F9/30

Abstract: Techniques are described for power reduction in a computer processor based on detection of whether data destined for input to an arithmetic logic unit (ALU) has a particular value. The data is written to a register prior to performing an arithmetic or logical operation using the data as an operand. Depending on a timing of when the data is supplied to the register, the determination is made before or after the data is written to the register, and a memory associated with the register is updated with a result of the determination. Contents of the memory are used to make a decision whether to allow the ALU to perform the arithmetic or logical operation. The memory can be implemented as a non-architectural register.