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公开(公告)号：US12137161B2
公开(公告)日：2024-11-05
申请号：US17548146
申请日：2021-12-10
Applicant: Amazon Technologies, Inc.
Inventor： Ali Ghassan Saidi , Adi Habusha
Abstract: A host device may include an interconnect, a host memory, and a set of processor cores. A processor core may execute a VM assigned to a cryptographic key and may send a request to access a physical address in the host memory toward the interconnect. An enforcer device may receive the request and extract a key identifier from the request. The enforcer device may determine whether to allow the request to access the physical address via the interconnect based on the key identifier and a list of allowed keys stored on the enforcer device. If the enforcer device determines to not allow the request to access, the enforcer device may modify the physical address and/or the key identifier of the request.
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公开(公告)号：US11836103B1
公开(公告)日：2023-12-05
申请号：US17455138
申请日：2021-11-16
Applicant: Amazon Technologies, Inc.
Inventor： Guy Nakibly , Roi Ben Haim , Erez Izenberg , Adi Habusha , Yaniv Shapira
CPC classification number: G06F13/4027 , G06F13/4221 , G06F2213/0026
Abstract: Systems and methods are provided to differentiate different types of traffic going through the same physical channel such that the traffic flow for different traffic types does not impact each other. The physical channel can be configured to support a plurality of virtual channels. Each transaction that needs to be communicated through the physical channel can be classified into a certain traffic type, and each traffic type can be assigned to a virtual channel. Each transaction can be communicated on a respective virtual channel based on the corresponding traffic type. If the traffic flow through a first virtual channel for a transaction slows down, the traffic flow through a second virtual channel for another transaction can continue without getting impacted by the slow down on the first virtual channel.
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公开(公告)号：US20230188338A1
公开(公告)日：2023-06-15
申请号：US17548146
申请日：2021-12-10
Applicant: Amazon Technologies, Inc.
Inventor： Ali Ghassan Saidi , Adi Habusha
CPC classification number: H04L9/0891 , G06F9/45558 , G06F21/72 , G06F2009/45587 , G06F2009/45579
Abstract: A host device may include an interconnect, a host memory, and a set of processor cores. A processor core may execute a VM assigned to a cryptographic key and may send a request to access a physical address in the host memory toward the interconnect. An enforcer device may receive the request and extract a key identifier from the request. The enforcer device may determine whether to allow the request to access the physical address via the interconnect based on the key identifier and a list of allowed keys stored on the enforcer device. If the enforcer device determines to not allow the request to access, the enforcer device may modify the physical address and/or the key identifier of the request.
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公开(公告)号：US11645075B1
公开(公告)日：2023-05-09
申请号：US17305152
申请日：2021-06-30
Applicant: Amazon Technologies, Inc.
Inventor： Barak Wasserstrom , Adi Habusha , Ron Diamant , Erez Sabbag
CPC classification number: G06F9/30058 , G06F9/3836 , G06F9/45558 , G06K9/6256 , G06N3/08
Abstract: Execution flows of a program can be characterized by a series of execution events. The rates at which these execution events occur for a particular program can be collected periodically, and the execution events statistics can be utilized for both training a machine learning model, and later on for making classification inferences to determine whether a program run contains any abnormality. When an abnormality is encountered, an alert can be generated and provided to supervisory logic of a computing system to indicate that an abnormal program flow has been detected.
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公开(公告)号：US10768965B1
公开(公告)日：2020-09-08
申请号：US15969684
申请日：2018-05-02
Applicant: Amazon Technologies, Inc.
Inventor： Adi Habusha , Ali Ghassan Saidi
IPC: G06F12/02 , G06F9/455 , G06F12/1036
Abstract: Systems and methods are provided to reduce the number of redundant copy operations performed as part of a live migration of a virtual machine executing a guest. A hypervisor can queue the copy operations in a processing engine. While pre-copying for the live migration of the VM, the guest may continue to write to the pages. In one embodiment, the processing engine may clear a dirty page just before performing the copy operation of the modified page to a target device, thus extending the window of time to capture any future writes to that page.
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Patent Agency Ranking
公开(公告)号：US09959227B1
公开(公告)日：2018-05-01
申请号：US14971759
申请日：2015-12-16
Applicant: Amazon Technologies, Inc.
Inventor： Ron Diamant , Georgy Machulsky , Adi Habusha
IPC: G06F13/00 , G06F13/28 , G06F12/0862
CPC classification number: G06F13/28 , G06F12/0862 , G06F2212/6028
Abstract: Apparatus and methods are disclosed herein for reducing I/O latency when accessing data using a direct memory access (DMA) engine with a parser. A DMA descriptor indicating memory buffer location can be stored in cache. A DMA descriptor read command is generated and can include a prefetch command. A descriptor with the indicator can be communicated to the DMA engine in response to the read. A second parser can detect the descriptor communication, parse the descriptor, and can prefetch data from memory to cache while the descriptor is being communicated to the DMA engine and/or parsed by the DMA engine parser. When the DMA engine parses the descriptor, data can be accessed from cache rather than memory, to decrease latency.
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公开(公告)号：US09804988B1
公开(公告)日：2017-10-31
申请号：US14928990
申请日：2015-10-30
Applicant: Amazon Technologies, Inc.
Inventor： Hani Ayoub , Adi Habusha , Ronen Shitrit
CPC classification number: G06F13/4022 , G06F13/28 , G06F13/404 , G06F13/4282 , G06F2213/0024 , G06F2213/0026
Abstract: A method of transferring data between a host and a PCI device is disclosed. The method comprises mapping a fixed memory-mapping control block in a host memory of the host to a control register of a memory-mapping unit of the PCI device; mapping a dynamic data-access memory block in the host memory to a default memory block in a memory of the PCI device, wherein the memory-mapping unit translates an address between the dynamic data-access memory block and a memory block in the memory of the PCI device; and dynamically modifying a value in the control register of the memory-mapping unit through the fixed memory-mapping control block such that an address of the dynamic data-access memory block in the host memory is translated to a different address in the memory of the PCI device based on the modified value in the control register of the memory-mapping unit.
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公开(公告)号：US09411731B2
公开(公告)日：2016-08-09
申请号：US14829410
申请日：2015-08-18
Applicant: Amazon Technologies, Inc.
Inventor： Adi Habusha , Gil Stoler , Said Bshara , Nafea Bshara
CPC classification number: G06F12/0828 , G06F12/0831 , G06F12/0833 , G06F12/0855 , G06F2212/62 , G06F2212/621 , G11C7/1072
Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.
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公开(公告)号：US12164445B1
公开(公告)日：2024-12-10
申请号：US17592233
申请日：2022-02-03
Applicant: Amazon Technologies, Inc.
Inventor： Ofer Naaman , Itai Avron , Adi Habusha , Aviv Bakal , Leonid Froenchenko
Abstract: The coherency of data can be maintained even for accelerators that may not directly support, or be part of, a coherency protocol or domain. A pair of agents can be utilized that include an application accelerator agent and a coherent agent. The coherent agent can support the coherency protocol and track coherency information for data in the coherency environment, to ensure coherent access to the data. The application accelerator agent can work with the coherent agent to obtain the data according to the coherency protocol, then perform operations on the data corresponding to a respective application or process. Such an approach enables an accelerator to function like a processor or processor core that otherwise supports the coherency protocol and is part of the coherency domain. A single coherent agent can be used to maintain coherency information for multiple other components or agents.
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公开(公告)号：US11868204B1
公开(公告)日：2024-01-09
申请号：US17548270
申请日：2021-12-10
Applicant: Amazon Technologies, Inc.
Inventor： Ofer Naaman , Osnat Katz , Nir Bar-Or , Adi Habusha
CPC classification number: G06F11/079 , G06F11/073 , G06F11/0751
Abstract: A system includes an obsolete cache-line vector having a plurality of memory elements, wherein each memory element has a one-to-one correspondence to a cache line entry of a cache memory. The vector can capture cache line errors that occur at different times from an error detection logic associated with the cache memory. A counter can be coupled to the obsolete cache-line vector for tracking how many of the memory elements in the vector are activated. When a predetermined threshold is reached, a threshold comparator can release a trigger for further analysis. An error events logger can be used to track all of the errors that occurred. The error events logger can also use a time stamp, which can assist the RAS system in analyzing a correlation between the errors, such as patterns that occur and time differences between the errors.
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