SEMICONDUCTOR DEVICE WITH EMBEDDED SEMICONDUCTOR DIE AND SUBSTRATE-TO-SUBSTRATE INTERCONNECTS

    公开(公告)号:US20190311991A1

    公开(公告)日:2019-10-10

    申请号:US16418079

    申请日:2019-05-21

    摘要: A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface and a bottom surface, a semiconductor die bonded to the top surface of the substrate, a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate, and a first conductive bump that is on the top surface of the substrate and is at least partially encapsulated by the first mold material. An extended substrate may be coupled to the substrate utilizing the first conductive bump. A second conductive bump may be formed on the bottom surface of the substrate, and a second mold material may encapsulate at least a portion of the second conductive bump and at least a portion of the bottom surface of the substrate. A third mold material may be formed between the first mold material and the extended substrate.

    Semiconductor device with embedded semiconductor die and substrate-to-substrate interconnects

    公开(公告)号:US10297552B2

    公开(公告)日:2019-05-21

    申请号:US15357551

    申请日:2016-11-21

    摘要: A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface and a bottom surface, a semiconductor die bonded to the top surface of the substrate, a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate, and a first conductive bump that is on the top surface of the substrate and is at least partially encapsulated by the first mold material. An extended substrate may be coupled to the substrate utilizing the first conductive bump. A second conductive bump may be formed on the bottom surface of the substrate, and a second mold material may encapsulate at least a portion of the second conductive bump and at least a portion of the bottom surface of the substrate. A third mold material may be formed between the first mold material and the extended substrate.

    SEMICONDUCTOR PACKAGE STRUCTURE FOR IMPROVING DIE WARPAGE AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20200185338A1

    公开(公告)日:2020-06-11

    申请号:US16707411

    申请日:2019-12-09

    IPC分类号: H01L23/00

    摘要: A semiconductor die package includes a semiconductor die, a film for improving die warpage bonded to a first face of the semiconductor die, a plurality of electrically conductive bumps formed on a second face of the semiconductor die, a substrate onto which the electrically conductive bumps of the second face of the semiconductor die are bonded to electrically connect the semiconductor die and the substrate, and a mold compound applied these components to form an exposed surface of the semiconductor die package that is coplanar with an exposed surface of the film.