公开(公告)号：US09503109B2

公开(公告)日：2016-11-22

申请号：US14726913

申请日：2015-06-01

Applicant: ANALOG DEVICES GLOBAL

Inventor： David J. McLaurin ,  Christopher W. Angell ,  Michael F. Keaveney

IPC: H03K3/013 ,  H03L7/081 ,  H03L7/197 ,  H03L7/085 ,  H03L7/10 ,  H03L7/199 ,  H03L7/23

CPC classification number: H03L7/1976 ,  H03L7/085 ,  H03L7/104 ,  H03L7/199 ,  H03L7/23

Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.

公开(公告)号：US20180062675A1

公开(公告)日：2018-03-01

申请号：US15801874

申请日：2017-11-02

Applicant: Analog Devices Global

Inventor： Patrick Pratt ,  Peadar Antony Forbes ,  David J. McLaurin ,  Martin McCormick

IPC: H04B1/04

CPC classification number: H04B1/0475 ,  H04B1/525

Abstract: Transmitter noise cancellation may be applied on a channel by channel basis to active channels of an incoming radio frequency signal received at a receiver. A noise cancellation filter may be provided for each active channel in a predetermined signal band. Applying noise cancellation on a per active channel basis instead of to the entire receive band may substantially reduce the filtering requirement and number of filter coefficients or taps to save power and reduce manufacturing costs. Channelized transmitter noise cancellers, multi transmitter-receiver cross coupling cancellers, and hybrid full signal band and channelized transmitter noise cancellers are also provided.

公开(公告)号：US20150263742A1

公开(公告)日：2015-09-17

申请号：US14726913

申请日：2015-06-01

Applicant: ANALOG DEVICES GLOBAL

Inventor： David J. McLaurin ,  Christopher W. Angell ,  Michael F. Keaveney

IPC: H03L7/197 ,  H03L7/199

CPC classification number: H03L7/1976 ,  H03L7/085 ,  H03L7/104 ,  H03L7/199 ,  H03L7/23

Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.

Abstract translation: 提供了用于同步锁相环（PLL）的装置和方法。 在某些实现中，分数N合成器包括PLL和控制PLL的分频值的控制电路。 控制电路包括内插器，复位相位调整计算器和同步电路。 内插器可以控制PLL分频值的小数部分。 复位相位调整计算器可以包括一个计数器，用于对分数N合成器的初始化后的参考时钟信号的周期数进行计数，并且复位相位调整计算器可以基于计数产生相位调整信号。 同步电路可以响应于同步信号来同步PLL，并且可以校正由相位调整信号指示的同步相位误差。

公开(公告)号：US09831898B2

公开(公告)日：2017-11-28

申请号：US13801130

申请日：2013-03-13

Applicant: Analog Devices Global

Inventor： Patrick Pratt ,  Peadar Antony Forbes ,  David J. McLaurin ,  Martin McCormick

IPC: H04B1/00 ,  H04B1/04 ,  H04B1/525

CPC classification number: H04B1/0475 ,  H04B1/525

Abstract: Transmitter noise cancellation may be applied on a channel by channel basis to active channels of an incoming radio frequency signal received at a receiver. A noise cancellation filter may be provided for each active channel in a predetermined signal band. Applying noise cancellation on a per active channel basis instead of to the entire receive band may substantially reduce the filtering requirement and number of filter coefficients or taps to save power and reduce manufacturing costs. Channelized transmitter noise cancellers, multi transmitter-receiver cross coupling cancellers, and hybrid full signal band and channelized transmitter noise cancellers are also provided.

公开(公告)号：US09124292B2

公开(公告)日：2015-09-01

申请号：US14537532

申请日：2014-11-10

Applicant: ANALOG DEVICES GLOBAL

Inventor： Zhao Li ,  Shipra Bhal ,  Kevin Glenn Gard ,  David Nelson Alldred ,  Christopher Mayer ,  Trevor Clifford Caldwell ,  David J. McLaurin ,  Victor Kozlov

IPC: H03M1/10 ,  H03M3/00 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M3/384 ,  H03M1/00 ,  H03M1/1009 ,  H03M1/12 ,  H03M3/458

Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

Abstract translation: 用于模数转换器（ADC）的校准系统，内部ADC接收模拟输入并将模拟输入转换为数字多位数据。 该校准系统还包括一个参考混洗电路，它洗牌内部ADC的比较器参考值。 此外，校准系统包括校准电路，校准内部ADC的比较器。 校准系统包括基于数字多位数据测量幅度的数字块。 此外，校准系统包括基于数字块的输出来控制校准电路的校准逻辑。