公开(公告)号：US07560326B2

公开(公告)日：2009-07-14

申请号：US11381810

申请日：2006-05-05

申请人： Anda C. Mocuta ,  Dureseti Chidambarrao ,  Ricardo A. Donaton ,  David M. Onsongo ,  Kern Rim

发明人： Anda C. Mocuta ,  Dureseti Chidambarrao ,  Ricardo A. Donaton ,  David M. Onsongo ,  Kern Rim

IPC分类号： H01L21/8234 ,  H01L31/0392

CPC分类号： H01L21/823807 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/78687

摘要： A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occurrence and propagation of misfit dislocations in the structure. The stress receiving layer is silicon (Si), the stress inducing layer is silicon-germanium (SiGe) and the material is carbon which is provided by doping the layers during formation of the device. The carbon can be doped throughout the whole of the SiGe layer also.

摘要翻译： 一种制造半导体器件的半导体结构和方法，特别是NFET器件。 这些装置包括在应力诱导层上提供的应力接收层，其中在其间的界面处的材料减少了结构中失配位错的发生和传播。 应力接收层是硅（Si），应力诱导层是硅锗（SiGe），并且材料是在形成器件期间通过掺杂层提供的碳。 也可以在整个SiGe层中掺杂碳。

公开(公告)号：US20080179636A1

公开(公告)日：2008-07-31

申请号：US11307224

申请日：2007-01-27

申请人： Dureseti Chidambarrao ,  Effendi Leobandung ,  Anda C. Mocuta ,  Dan M. Mocuta ,  David M. Onsongo ,  Carl J. Radens

发明人： Dureseti Chidambarrao ,  Effendi Leobandung ,  Anda C. Mocuta ,  Dan M. Mocuta ,  David M. Onsongo ,  Carl J. Radens

IPC分类号： H01L29/04 ,  H01L21/335 ,  H01L21/8238

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7849

摘要： The present invention relates to high performance n-channel field effect transistors (n-FETs) that each contains a strained semiconductor channel, and methods for forming such n-FETs by using buried pseudomorphic layers that contain pseudomorphically generated compressive strain.

摘要翻译： 本发明涉及各自包含应变半导体通道的高性能n沟道场效应晶体管（n-FET），以及通过使用包含假象形成的压缩应变的掩埋伪晶层来形成这种n-FET的方法。

公开(公告)号：US07615418B2

公开(公告)日：2009-11-10

申请号：US11380688

申请日：2006-04-28

申请人： Dureseti Chidambarrao ,  Ricardo A. Donaton ,  William K. Henson ,  Kern Rim

发明人： Dureseti Chidambarrao ,  Ricardo A. Donaton ,  William K. Henson ,  Kern Rim

IPC分类号： H01L21/8232 ,  H01L21/335

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848 ,  Y10S438/938

摘要： A semiconductor structure and method of manufacturing and more particularly a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET. The PFET region and the NFET region having a different sized gate to vary the device performance of the NFET and the PFET.

摘要翻译： 一种半导体结构和制造方法，更具体地说是具有嵌入在PFET的栅极和源极/漏极区域中的应力诱导材料的CMOS器件。 PFET区域和NFET区域具有不同尺寸的栅极，以改变NFET和PFET的器件性能。

公开(公告)号：US07791144B2

公开(公告)日：2010-09-07

申请号：US12506770

申请日：2009-07-21

申请人： Dureseti Chidambarrao ,  Ricardo A. Donaton ,  William K. Henson ,  Kern Rim

发明人： Dureseti Chidambarrao ,  Ricardo A. Donaton ,  William K. Henson ,  Kern Rim

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848 ,  Y10S438/938

摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.

摘要翻译： 本发明涉及一种制造半导体结构和方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极中的应力诱导材料以及PFET和NFET沟道的变化的厚度。 在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。

公开(公告)号：US20100013024A1

公开(公告)日：2010-01-21

申请号：US12506770

申请日：2009-07-21

申请人： Dureseti Chidambarrao ,  Ricardo A. Donaton ,  William K. Henson ,  Kern Rim

发明人： Dureseti Chidambarrao ,  Ricardo A. Donaton ,  William K. Henson ,  Kern Rim

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848 ,  Y10S438/938

摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.

摘要翻译： 本发明涉及半导体结构和制造方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极区域中以及PFET和NFET沟道的变化厚度的应力诱导材料。 在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。

公开(公告)号：US07608489B2

公开(公告)日：2009-10-27

申请号：US11380689

申请日：2006-04-28

申请人： Dureseti Chidambarrao ,  Ricardo A. Donaton ,  William K. Henson ,  Kern Rim

发明人： Dureseti Chidambarrao ,  Ricardo A. Donaton ,  William K. Henson ,  Kern Rim

IPC分类号： H01L21/8232 ,  H01L21/335

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848 ,  Y10S438/938

摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.

摘要翻译： 本发明涉及半导体结构和制造方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极区域中以及PFET和NFET沟道的变化厚度的应力诱导材料。 在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。

公开(公告)号：US08429576B2

公开(公告)日：2013-04-23

申请号：US13471789

申请日：2012-05-15

申请人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

发明人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC分类号： G06F17/50

CPC分类号： G01R31/26 ,  G06F17/5045

摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

公开(公告)号：US08239790B2

公开(公告)日：2012-08-07

申请号：US13216362

申请日：2011-08-24

申请人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

发明人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC分类号： G06F17/50

CPC分类号： G01R31/26 ,  G06F17/5045

摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

摘要翻译： 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

公开(公告)号：US07705345B2

公开(公告)日：2010-04-27

申请号：US10751916

申请日：2004-01-07

申请人： Stephen W. Bedell ,  Kevin K. Chan ,  Dureseti Chidambarrao ,  Silke H. Christianson ,  Jack O. Chu ,  Anthony G. Domenicucci ,  Kam-Leung Lee ,  Anda C. Mocuta ,  John A. Ott ,  Qiqing C. Ouyang

发明人： Stephen W. Bedell ,  Kevin K. Chan ,  Dureseti Chidambarrao ,  Silke H. Christianson ,  Jack O. Chu ,  Anthony G. Domenicucci ,  Kam-Leung Lee ,  Anda C. Mocuta ,  John A. Ott ,  Qiqing C. Ouyang

IPC分类号： H01L29/06 ,  H01L31/072

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.

摘要翻译： 应变Fin场效应晶体管（FinFET）（及其形成方法）包括具有侧壁的松弛的第一材料和形成在第一材料的侧壁上的应变的第二材料。 松弛的第一材料和应变的第二材料形成FinFET的鳍。

公开(公告)号：US20110307846A1

公开(公告)日：2011-12-15

申请号：US13216362

申请日：2011-08-24

申请人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

发明人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC分类号： G06F17/50

CPC分类号： G01R31/26 ,  G06F17/5045

摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

摘要翻译： 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。