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    Method for preventing sidewall consumption during oxidation of SGOI islands
    2.
    发明授权
    Method for preventing sidewall consumption during oxidation of SGOI islands 失效
    防止SGOI岛氧化期间侧壁消耗的方法

    公开(公告)号：US07067400B2

    公开(公告)日：2006-06-27

    申请号：US10943354

    申请日：2004-09-17

    申请人： Stephen W. Bedell ,  Anda C. Mocuta

    发明人： Stephen W. Bedell ,  Anda C. Mocuta

    IPC分类号： H01L21/20 ,  H01L21/36

    CPC分类号： H01L21/32105 ,  H01L21/84 ,  Y10S438/967

    摘要： A method of forming a substantially relaxed SiGe-on-insulator substrate in which the consumption of the sidewalls of SiGe-containing island structures during a high temperature relaxation annealing is substantially prevented or eliminated is provided. The method serves to maintain the original lateral dimensions of the patterned SiGe-containing islands, while providing a uniform and homogeneous Ge fraction of the islands that is independent of each island size. The method includes forming an oxidation mask on at least sidewalls of a SiGe-containing island structure that is located on a barrier layer that is resistant to Ge diffusion. A heating step is then employed to cause at least relaxation within the SiGe-containing island structure. The presence of the oxidation mask substantially prevents consumption of at least the sidewalls of the SiGe-containing island structure during the heating step.

    摘要翻译： 提供了一种形成基本上松弛的绝缘体上硅衬底的方法，其中基本上防止或消除了在高温松弛退火期间消耗含SiGe的岛结构的侧壁。 该方法用于保持图案化含SiGe岛的原始横向尺寸，同时提供独立于每个岛尺寸的岛的均匀且均匀的Ge部分。 该方法包括在至少位于阻挡层上的含SiGe的岛状结构的侧壁上形成氧化掩模，所述阻挡层具有抵抗Ge扩散的作用。 然后采用加热步骤在含SiGe的岛结构内引起至少松弛。 氧化掩模的存在基本上防止在加热步骤期间消耗至少含SiGe的岛结构的侧壁。

    High-quality SGOI by annealing near the alloy melting point
    3.
    发明授权
    High-quality SGOI by annealing near the alloy melting point 失效
    高品质SGOI通过在合金熔点附近退火

    公开(公告)号：US07679141B2

    公开(公告)日：2010-03-16

    申请号：US12027561

    申请日：2008-02-07

    申请人： Stephen W. Bedell ,  Huajie Chen ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Richard J. Murphy ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  Huajie Chen ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Richard J. Murphy ,  Devendra K. Sadana

    IPC分类号： H01L31/392

    CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76254 ,  H01L29/1054

    摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.

    摘要翻译： 提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。 该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。 然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。 加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。 此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。 在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。 该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

    Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
    5.
    发明授权
    Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer 有权
    通过弹性应变转移形成的超薄，高品质应变绝缘体上的绝缘体

    公开(公告)号：US07442993B2

    公开(公告)日：2008-10-28

    申请号：US11293774

    申请日：2005-12-02

    申请人： Stephen W. Bedell ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Effendi Leobandung ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Effendi Leobandung ,  Devendra K. Sadana

    IPC分类号： H01L31/392

    CPC分类号： H01L29/78696 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/76251 ,  H01L29/7842

    摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.

    摘要翻译： 提供了一种在绝缘层上形成包括第一应变半导体层的半导体结构的方法，其中第一应变半导体层相对较薄（小于约）并且具有低缺陷密度（堆垛层错和穿线缺陷）。 本发明的方法开始于在包括位于绝缘层顶部的第一半导体层的结构上形成应力提供层，例如SiGe合金层。 然后将应力提供层和第一半导体层图案化成至少一个岛，然后将含有至少一个岛的结构加热到使得应力转移从应力提供层到第一半导体层的温度。 在应变转移之后，将应力提供层从结构上去除，以形成直接位于所述绝缘层顶部的第一应变半导体岛层。

    Electron microscope magnification standard providing precise calibration in the magnification range 5000X-2000,000X
    7.
    发明授权
    Electron microscope magnification standard providing precise calibration in the magnification range 5000X-2000,000X 失效
    电子显微镜放大标准提供5000X-2000,000X倍率范围内的精确校准

    公开(公告)号：US06875982B2

    公开(公告)日：2005-04-05

    申请号：US10604989

    申请日：2003-08-29

    申请人： Stephen W. Bedell ,  John Bruley ,  Anthony G. Domenicucci ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  John Bruley ,  Anthony G. Domenicucci ,  Devendra K. Sadana

    IPC分类号： G01N1/28 ,  G01N23/04 ,  H01J37/26

    CPC分类号： G01N23/04 ,  G01N2001/2893 ,  H01J37/261 ,  H01J2237/2826

    摘要： A method and calibration standard for fabricating on a single substrate a series of crystalline pairs such that the d-spacing difference between the pairs will generate Moire fringes of the correct spacings to optimally calibrate the magnification settings of an electron microscope over a variety of magnification settings in the range of 5000× to 200,000×. The invention enables the tailoring of Moire fringe spacings to a desired magnification setting for calibration purposes by fabricating a series of patterns on a single substrate whereby each magnification setting is easily calibrated using a specific SGOI structure that is selected by a simple x-y translation across the top plan surface of the SGOI structure, therein eliminating the need for removing calibration samples in and out of the electron microscope. The method and calibration standard may be used for calibrating electron microscopes, such as, scanning transmission electron microscopes and transmission electron microscopes.

    摘要翻译： 一种用于在单个基板上制造一系列晶体对的方法和校准标准，使得对之间的d间距差会产生正确间隔的莫尔条纹，以便通过各种放大设置最佳地校准电子显微镜的放大倍率设置 在5000x到200,000x的范围内。 通过在单个基板上制造一系列图案，本发明可以通过在单个基板上制造一系列图案来将莫尔条纹间距定制到所需的放大倍率设置，从而可以使用特定的SGOI结构轻松校准每个放大倍数设置，该SGOI结构通过顶部的简单xy平移 SGOI结构的平面表面，其中不需要将校准样品移入和移出电子显微镜。 该方法和校准标准可用于校准电子显微镜，例如扫描透射电子显微镜和透射电子显微镜。

    High-quality SGOI by annealing near the alloy melting point
    10.
    发明授权
    High-quality SGOI by annealing near the alloy melting point 有权
    高品质SGOI通过在合金熔点附近退火

    公开(公告)号：US07348253B2

    公开(公告)日：2008-03-25

    申请号：US10855915

    申请日：2004-05-27

    申请人： Stephen W. Bedell ,  Huajie Chen ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Richard J. Murphy ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  Huajie Chen ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Richard J. Murphy ,  Devendra K. Sadana

    IPC分类号： H01L21/84

    CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76254 ,  H01L29/1054

    摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.

    摘要翻译： 提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。 该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。 然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。 加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。 此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。 在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。 该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。