公开(公告)号：US5784573A

公开(公告)日：1998-07-21

申请号：US334470

申请日：1994-11-04

申请人： Andre Szczepanek ,  Denis R. Beaudoin

发明人： Andre Szczepanek ,  Denis R. Beaudoin

IPC分类号： H04L12/413 ,  H04L12/44 ,  H04L25/49 ,  H04L29/06 ,  H04L29/08 ,  G06F13/42 ,  H04L12/28

CPC分类号： H04L29/06 ,  H04L12/40013 ,  H04L25/4908 ,  H04L12/40143 ,  H04L12/413 ,  H04L12/44 ,  H04L69/18 ,  H04L69/324

摘要： A local area network ("LAN") controller operable in an IEEE 802.3u network and an IEEE 802.12 network. A common physical connector is used for both standards, attached to an attachment medium such as a card. An 802.3u circuit is attached to the card, implementing the following 802.3u functions: A media access controller ("MAC") layer, and a physical media independent ("PMI") layer that provides the IEEE 802.3u media independent interface ("MII"). An 802.12 circuit is also attached to the card, implementing the following IEEE 802.12 functions: An LLC layer, an MAC layer, and a PMI layer, providing an MII to a device implementing an 802.12 physical media dependent ("PMD") layer. A circuit coupled to the 802.12 circuit multiplexes, according to a predetermined strategy, 802.12 PMI to PMD signals over the physical connector and, alternatively, communicates 802.3u MII signals between the 802.3u circuit and the physical connector.

摘要翻译： 在IEEE 802.3u网络和IEEE 802.12网络中可操作的局域网（“LAN”）控制器。 通常的物理连接器用于两个标准，附接到诸如卡的附接介质。 802.3u电路连接到卡，实现以下802.3u功能：介质访问控制器（“MAC”）层，以及物理介质无关（“PMI”）层，提供IEEE 802.3u媒体独立接口（“ MII“）。 802.16电路也被附加到卡上，实现以下IEEE 802.12功能：LLC层，MAC层和PMI层，向实现802.12物理介质依赖（“PMD”）层的设备提供MII。 耦合到802.12电路的电路根据预定的策略将802.12 PMI多路复用到物理连接器上的PMD信号，并且或者在802.3u电路和物理连接器之间传送802.3u MII信号。

公开(公告)号：US5715419A

公开(公告)日：1998-02-03

申请号：US446019

申请日：1989-12-05

申请人： Andre Szczepanek ,  Keith Balmer ,  Philip John Moyse ,  Denis Roland Beaudoin

发明人： Andre Szczepanek ,  Keith Balmer ,  Philip John Moyse ,  Denis Roland Beaudoin

IPC分类号： G06F9/355 ,  G06F12/06 ,  G06F9/30

CPC分类号： G06F9/342 ,  G06F12/0623

摘要： A data communications system memory interface circuit (32) is provided which operates within an adapter circuit (10). Adapter circuit (10) comprises a communications processor (28), a system interface (30) and a protocol handler (20) coupled together by an adapter bus (26). Communications processor (28) accesses an external memory (38) through a memory interface (32). Memory interface (32) comprises a map register circuit (36) which comprises a number of map registers (44 through 56). The map registers (44 through 56) each are operable to store a portion of a twenty bit address which may be selected by a multiplexer (42) responsive to control signals generated by a control logic circuit (40). The address portion stored in the map registers (44 through 56) are added to a remaining portion of an address to form a complete twenty bit remapped address. In this manner, communications processor (28), using a sixteen bit internal address bus, can access a twenty bit addressable memory space within external memory (38). System interface (30) comprises an address register circuit (34) which allows for the accessing of arbitrary twenty bit addresses or the accessing of addresses using page address numbers and offset values. The protocol handler (20) comprises a page address register (24) which allows for the accessing of external memory (38) on one kilobyte page boundaries.

摘要翻译： 提供了在适配器电路（10）内操作的数据通信系统存储器接口电路（32）。 适配器电路（10）包括通过适配器总线（26）耦合在一起的通信处理器（28），系统接口（30）和协议处理器（20）。 通信处理器（28）通过存储器接口（32）访问外部存储器（38）。 存储器接口（32）包括地图寄存器电路（36），其包括多个映射寄存器（44至56）。 每个映射寄存器（44至56）可操作以响应于由控制逻辑电路（40）产生的控制信号来存储可由多路复用器（42）选择的二十位地址的一部分。 存储在映射寄存器（44至56）中的地址部分被添加到地址的剩余部分以形成完整的二十位重映射地址。 以这种方式，使用十六位内部地址总线的通信处理器（28）可以访问外部存储器（38）内的二十位可寻址存储器空间。 系统接口（30）包括地址寄存器电路（34），其允许使用页地址号和偏移值访问任意二十位地址或访问地址。 协议处理器（20）包括页面地址寄存器（24），其允许在一个千字节页面边界上访问外部存储器（38）。

公开(公告)号：US5265228A

公开(公告)日：1993-11-23

申请号：US446505

申请日：1989-12-05

申请人： Denis R. Beaudoin ,  Andre Szczepanek

发明人： Denis R. Beaudoin ,  Andre Szczepanek

IPC分类号： G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F12/06

CPC分类号： G06F13/1673 ,  G06F13/28 ,  G06F13/4059

摘要： The present invention includes a data transfer system (28) which includes a first bus (32) and a second bus (34) wherein both buses are bidirectionally connected to a first memory (30). Similarly, a third bus (42) and a fourth bus (44) are bidirectionally connected to a second memory (40). A plurality of data cells (50a through 50h) are provided for intermediate storage when units of information are transferred between first and second memories (30 and 40). A first pointer (37) is under control of first pointer circuit (36) and first control circuit (38) such that buses (32 and 34) may have access to selected ones of the plurality of data cells (50a through 50h). Similarly, a second pointer (47) is under control of second pointer circuit (46) and second control circuit (48) such that third and fourth buses (42 and 44) may have access to the plurality of data cells (50a through 50h).

摘要翻译： 本发明包括数据传输系统（28），其包括第一总线（32）和第二总线（34），其中两个总线双向连接到第一存储器（30）。 类似地，第三总线（42）和第四总线（44）双向地连接到第二存储器（40）。 当在第一和第二存储器（30和40）之间传送信息单元时，提供多个数据单元（50a至50h）用于中间存储器。 第一指针（37）在第一指针电路（36）和第一控制电路（38）的控制下，使得总线（32和34）可以访问多个数据单元（50a至50h）中的选定数据单元。 类似地，第二指针（47）在第二指针电路（46）和第二控制电路（48）的控制下，使得第三和第四总线（42和44）可以访问多个数据单元（50a至50h） 。

公开(公告)号：US4698753A

公开(公告)日：1987-10-06

申请号：US440380

申请日：1982-11-09

申请人： Stephen J. Hubbins ,  David G. England ,  Andre Szczepanek ,  David Norvall

发明人： Stephen J. Hubbins ,  David G. England ,  Andre Szczepanek ,  David Norvall

IPC分类号： G06F13/18 ,  G06F15/167 ,  G06F15/16

CPC分类号： G06F15/167 ,  G06F13/18

摘要： A single chip multiprocessor interface device for interfacing between two processors by connection to their bus systems, the device having a random access memory selectively accessible by the processors under the control of an arbitration latch. The arbitration latch has a bistable device the state of which determines which processor has access to the memory. The outputs of the bistable device have threshold devices which have threshold levels higher than the signal outputs of the bistable device when it is in a metastable state, so that there is no possibility that both processors could have access to the memory at the same time. Data and address registers for the two processors are selectively connectible to the random access memory through multiplexers controlled by the arbitration latch. Mode control inputs can set the device into a "stand alone" mode, a "master" mode and a "slave" mode; several devices can be used in parallel for bus systems more than one byte wide with one device the master and the others slaves. Control and status registers for each processor input enable the generation of interrupts when certain conditions are met.

摘要翻译： 一种单芯片多处理器接口设备，用于通过连接到它们的总线系统来在两个处理器之间进行接口，该设备具有由仲裁锁存器控制下的处理器可选择地访问的随机存取存储器。 仲裁锁存器具有双稳态器件，其状态确定哪个处理器可以访问存储器。 双稳态器件的输出具有阈值电平，其阈值电平在双稳态器件处于亚稳态时具有高于双稳态器件的信号输出的阈值电平，因此两个处理器都不可能同时访问存储器。 两个处理器的数据和地址寄存器通过由仲裁锁存器控制的多路复用器选择性地连接到随机存取存储器。 模式控制输入可以将设备设置为“独立”模式，“主”模式和“从”模式; 对于一个以上的字节宽度的总线系统，可以并行使用多个器件，一个器件是主器件和其他器件。 每个处理器输入的控制和状态寄存器使得能够在满足某些条件时产生中断。

公开(公告)号：US20100172355A1

公开(公告)日：2010-07-08

申请号：US12726727

申请日：2010-03-18

申请人： Andre Szczepanek ,  Martin Yu Li ,  Steven P. Marshall ,  Travis M. Scheckel

发明人： Andre Szczepanek ,  Martin Yu Li ,  Steven P. Marshall ,  Travis M. Scheckel

IPC分类号： H04L12/56

CPC分类号： H04L49/901 ,  H04L12/18 ,  H04L49/90 ,  H04L49/9042

摘要： High speed networking systems such as PCI-Express and Serial Rapid I/O are based on the exchange of packets across switched networks of high speed serial links. Information in the headers of these packets indicate the kind of transaction they represent. Queuing all received packets in a single queue will cause interactions between transaction types. Indirection can be used create the effect of multiple independent queues from a shared memory. This provides efficient centralized packet storage, while allowing independent processing of different transactions types.

摘要翻译： PCI-Express和串行快速I / O等高速网络系统是基于高速串行通信交换网络上的数据包交换。 这些数据包头中的信息表示它们所代表的交易类型。 在单个队列中排队所有接收到的数据包将导致事务类型之间的交互。 可以使用间接方式从共享内存中创建多个独立队列的效果。 这提供了有效的集中式分组存储，同时允许对不同事务类型的独立处理。

公开(公告)号：US20060268714A1

公开(公告)日：2006-11-30

申请号：US11383316

申请日：2006-05-15

申请人： Andre Szczepanek ,  Martin Li ,  Steven Marshall ,  Travis Scheckel

发明人： Andre Szczepanek ,  Martin Li ,  Steven Marshall ,  Travis Scheckel

IPC分类号： H04J1/16

CPC分类号： G01R31/31858 ,  H04L7/0041 ,  H04L7/0331 ,  H04L47/10 ,  H04L47/12 ,  H04L47/2441 ,  H04L47/266 ,  H04L47/41 ,  H04L49/90 ,  Y02D50/30

摘要： The management of flows can be simplified by only keeping unique flow information for locally important flows, and aggregating all other flows together. A flow control table of 16 entries, 15 unique and 1 aggregate is usually sufficient, particularly in systems where the traffic flows are relatively static. This greatly reduces the required logic for Xoff/Xon counters and timeout monitors Rather than every packet source checking each packet it sends, the flows needed by each unit are registered in the flow table and the table logic indicates to each unit whether it has any blocked flows.

摘要翻译： 流量的管理可以通过仅保留本地重要流量的独特流量信息，并将所有其他流量汇总在一起来简化。 16个条目，15个唯一和1个聚合的流量控制表通常是足够的，特别是在流量相对静态的系统中。 这大大减少了Xoff / Xon计数器和超时监视器所需的逻辑，而不是每个数据包源检查每个数据包发送的数据包，每个单元所需的流量都会记录在流程表中，表逻辑表明每个单元是否有任何阻塞 流动。

公开(公告)号：US07027447B2

公开(公告)日：2006-04-11

申请号：US09755825

申请日：2001-01-05

申请人： Iain Robertson ,  Andre Szczepanek ,  Denis R. Beaudoin

发明人： Iain Robertson ,  Andre Szczepanek ,  Denis R. Beaudoin

IPC分类号： H04L12/42

CPC分类号： H04L7/0012 ,  H04L7/005

摘要： A network switch system (10) is disclosed, in which a plurality of switch fabric devices (20) are interconnected according to a ring arrangement, each of the switch fabric devices (20) including therein switch interfaces (22) coupled to corresponding network switches (14, 16). Each switch fabric device includes a plurality of ring paths (24), each of which is associated with a receive ring interface (26R) and a transmit ring interface (26X). Each ring path (24) includes a circular buffer (44) having a plurality of entries, each of which is associated with valid logic (50). The valid logic (50) for each entry presents valid signals on valid lines (WV, RV) to the receive and transmit domains of the ring path (24), and receives signals on write and read word request lines (WRW, RDW) therefrom. Control of the access to the circular buffer (44) is made according to the write and read word request lines (WRW, RDW) for the corresponding entries of the circular buffer (44) to which write pointers and read pointers point. The write word request line (WRW) sets the valid lines (WV, RV) for the corresponding entry in each of the two clock domains, while the read word request line (RDW) resets these valid lines (WV, RV) for that entry. Differences in clock frequency between the receive and transmit clock domains are thus compensated, with a minimum latency.

摘要翻译： 公开了一种网络交换机系统（10），其中多个交换结构设备（20）根据环形布置互连，每个交换结构设备（20）包括其中耦合到相应网络交换机的交换接口（22） （14,16）。 每个交换结构设备包括多个环路（24），每个环路与接收环接口（26R）和发射环接口（26X）相关联。 每个环路（24）包括具有多个条目的循环缓冲器（44），每个条目与有效逻辑（50）相关联。 每个条目的有效逻辑（50）在有效的线路（WV，RV）上呈现环路径（24）的接收和发射域的有效信号，并且从写入和读取字请求线（WRW，RDW）接收信号 。 根据写指针和读指针指向的循环缓冲器（44）的对应条目的写和读字请求行（WRW，RDW），对对循环缓冲器（44）的访问进行控制。 写字请求行（WRW）为两个时钟域中的每个时钟域中的相应条目设置有效行（WV，RV），而读字请求行（RDW）为这个条目复位这些有效行（WV，RV） 。 因此，接收时钟和发送时钟域之间的时钟频率的差异将以最小的延迟进行补偿。

公开(公告)号：US5721841A

公开(公告)日：1998-02-24

申请号：US334299

申请日：1994-11-04

申请人： Andre Szczepanek

发明人： Andre Szczepanek

IPC分类号： G06F5/01 ,  G06F13/40 ,  G06F15/02

CPC分类号： G06F13/4018 ,  G06F5/01

摘要： A data alignmentation apparatus and method in a LAN adapter. The arrangement includes a data aligner mechanism and a transfer control mechanism that transfer data between this RAM and a PCI bus. A transfer control mechanism pre-calculates the control parameters for the aligner/data-pipe, creates the necessary byte enables for data transfers, and determines the member of transfers needed. This allows the data aligner to create a stream of data words for any arbitrary byte transfer with full PCI data streaming (one 32 bit word every PCI clock cycle). The Data Aligner provides a shifter and data-pipe that is used to convert the RAMs 64 bit words into PCIs 32 bit words. It is bidirectional and is used to convert 64 bit data from the RAM into 32 bit PCI word(s) and vice versa.

摘要翻译： LAN适配器中的数据对齐设备和方法。 该装置包括数据对准器机构和在该RAM与PCI总线之间传送数据的传送控制机构。 转移控制机构预先计算对齐器/数据管道的控制参数，创建数据传输所需的字节使能，并确定所需的传输成员。 这允许数据对齐器创建一个数据流流，用于任意字节传输，具有全PCI数据流（每PCI时钟周期一个32位字）。 数据对齐器提供了一个移位器和数据管道，用于将RAM 64位字转换为PCI 32位字。 它是双向的，用于将64位数据从RAM转换为32位PCI字，反之亦然。

公开(公告)号：US5717932A

公开(公告)日：1998-02-10

申请号：US334511

申请日：1994-11-04

申请人： Andre Szczepanek ,  Denis R. Beaudoin

发明人： Andre Szczepanek ,  Denis R. Beaudoin

IPC分类号： G06F13/24 ,  G06F13/00

CPC分类号： G06F13/24 ,  G06F2213/2404

摘要： A communications network adapter of the type coupling a computer, in which the computer includes a microprocessor, main memory and a system bus, that controls host interrupts in a manner to improve system performance. The adapter includes a buffer memory for storing data to be transferred between the bus an the network, and a transfer controller that controls the transfer of data between the main memory and the buffer memory and between the network and the buffer memory. The adapter also includes an interrupt controller that monitors predetermined events relating to data transfer between the computer and the network, and that causes the sending of interrupt signals to the microprocessor. Interrupt signals cause the microprocessor to initiate processing associated with the transfer of data between the computer and the network. According to one aspect of the invention the adapter includes an interrupt pacing timer that prevents the sending of interrupts to the microprocessor from the adapter for predetermined time after an interrupt acknowledgement signal is received from the microprocessor. According to another aspect of the invention an interrupt threshold counter is provided that prevents the sending of interrupts to the microprocessor until a predetermined plurality of frames are transmitted.

摘要翻译： 一种耦合计算机的通信网络适配器，其中计算机包括微处理器，主存储器和系统总线，其以提高系统性能的方式来控制主机中断。 适配器包括用于存储要在总线与网络之间传送的数据的缓冲存储器，以及控制主存储器和缓冲存储器之间以及网络与缓冲存储器之间的数据传送的传输控制器。 适配器还包括中断控制器，其监视与计算机和网络之间的数据传输相关的预定事件，并且导致向微处理器发送中断信号。 中断信号使微处理器发起与计算机和网络之间的数据传输相关的处理。 根据本发明的一个方面，适配器包括中断起搏定时器，其在从微处理器接收到中断确认信号之后的预定时间内防止从适配器向微处理器发送中断。 根据本发明的另一方面，提供了一种中断阈值计数器，其防止向微处理器发送中断，直到发送预定的多个帧。

公开(公告)号：US5497107A

公开(公告)日：1996-03-05

申请号：US61643

申请日：1993-05-13

申请人： Andre Szczepanek

发明人： Andre Szczepanek

IPC分类号： H03K19/173 ,  H03K19/177 ,  H04L29/04 ,  G06F7/38

CPC分类号： H03K19/17708

摘要： Circuitry 10 is provided that contains two (or more) PLA matrix structures 12, 14 which share at least some outputs and are interconnected with a common output structure 18, individual input 30 and output 42, 62 structures, and an appropriate controller 28 for selecting which PLA matrix structure 12, 14 is to be employed. A common input structure 16 may be interconnected with the PLA matrix structures 12, 14 employed. The controller 28 may also be employed to power-down the PLA matrix structures not employed. The controller 28 may be static and select one matrix structure until reset, or dynamic and change as a function of some control signal.

摘要翻译： 提供电路10，其包含两个（或更多个）PLA矩阵结构12,14，其共享至少一些输出并且与公共输出结构18，单个输入30和输出42,62结构互连，以及用于选择的适当的控制器28 将使用PLA基质结构12,14。 公共输入结构16可以与所采用的PLA矩阵结构12,14互连。 也可以使用控制器28对未采用的PLA矩阵结构进行掉电。 控制器28可以是静态的，并且选择一个矩阵结构直到复位，或者动态地作为一些控制信号的函数而改变。