公开(公告)号：US06908830B2

公开(公告)日：2005-06-21

申请号：US10604028

申请日：2003-06-23

申请人： Andrew Lu ,  Donald M. Odiwo ,  Roger J. Yerdon

发明人： Andrew Lu ,  Donald M. Odiwo ,  Roger J. Yerdon

IPC分类号： G03F7/20 ,  G03F9/00 ,  H01L21/66

CPC分类号： G03F9/7084 ,  G03F7/70475 ,  Y10S438/975

摘要： A method of repeatedly exposing a pattern across a wafer in a sequential stepping process is disclosed. The pattern that is exposed includes at least one alignment mark. Each time the exposing process is repeated, the current exposure overlaps a portion of the wafer where the pattern was previously exposed and thereby erases a previously exposed alignment mark by re-exposing an area of the wafer where the previously exposed alignment mark was located. After the exposing process is repeated across the wafer, alignment marks remain only in the last exposed areas of the wafer.

摘要翻译： 公开了一种在连续的步进过程中重复地在晶片上暴露图案的方法。 暴露的图案包括至少一个对准标记。 每次重复暴露过程时，当前的曝光与预先暴露图案的晶片的一部分重叠，从而通过再次暴露先前暴露的对准标记所位于的晶片的区域来擦除先前暴露的对准标记。 在跨晶片重复曝光过程之后，对准标记仅保留在晶片的最后曝光区域中。

公开(公告)号：US07475368B2

公开(公告)日：2009-01-06

申请号：US11336524

申请日：2006-01-20

申请人： Matthew S. Angyal ,  Giovanni Fiorenza ,  Habib Hichri ,  Andrew Lu ,  Dale C. McHerron ,  Conal E. Murray

发明人： Matthew S. Angyal ,  Giovanni Fiorenza ,  Habib Hichri ,  Andrew Lu ,  Dale C. McHerron ,  Conal E. Murray

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for each pixel. The deflection is predicated upon a planarizing of the pixel, and it is calculated while utilizing an algorithm that includes the fraction of the at least one constituent material. A series of deflections for the series of pixels may be mapped and evaluated.

摘要翻译： 用于分析电路设计的系统，方法和计算机程序产品提供将电路设计离散成一系列像素。 确定每个像素的至少一个构成材料的一部分。 还为每个像素确定偏转。 该偏转基于像素的平面化，并且在利用包括至少一个构成材料的分数的算法的同时进行计算。 可以映射和评估一系列像素的一系列偏转。

公开(公告)号：US06803668B2

公开(公告)日：2004-10-12

申请号：US10303501

申请日：2002-11-22

申请人： Karen L. Holloway ,  Andrew Lu ,  Qiang Wu

发明人： Karen L. Holloway ,  Andrew Lu ,  Qiang Wu

IPC分类号： H01L23544

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： An alignment mark structure for use upon a semiconductor substrate is disclosed. In an exemplary embodiment, the alignment mark structure includes a plurality of segments arranged in an alignment pattern, with each of the plurality of segments being formed from a base pattern created on the substrate. The base pattern includes a plurality of sizes, wherein each of the plurality of sizes of the base pattern is repeated throughout an entire length of each of the plurality of segments.

摘要翻译： 公开了一种在半导体衬底上使用的对准标记结构。 在示例性实施例中，对准标记结构包括以对准图案排列的多个段，多个段中的每一个由在衬底上形成的基本图案形成。 基本图案包括多个尺寸，其中基本图案的多个尺寸中的每一个在多个片段的每一个的整个长度上重复。

公开(公告)号：US20070174796A1

公开(公告)日：2007-07-26

申请号：US11336524

申请日：2006-01-20

申请人： Matthew Angyal ,  Giovanni Fiorenza ,  Habib Hichri ,  Andrew Lu ,  Dale McHerron ,  Conal Murray

发明人： Matthew Angyal ,  Giovanni Fiorenza ,  Habib Hichri ,  Andrew Lu ,  Dale McHerron ,  Conal Murray

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for each pixel. The deflection is predicated upon a planarizing of the pixel, and it is calculated while utilizing an algorithm that includes the fraction of the at least one constituent material. A series of deflections for the series of pixels may be mapped and evaluated.

摘要翻译： 用于分析电路设计的系统，方法和计算机程序产品提供将电路设计离散成一系列像素。 确定每个像素的至少一个构成材料的一部分。 还为每个像素确定偏转。 该偏转基于像素的平面化，并且在利用包括至少一个构成材料的分数的算法的同时进行计算。 可以映射和评估一系列像素的一系列偏转。

公开(公告)号：US06927472B2

公开(公告)日：2005-08-09

申请号：US09992344

申请日：2001-11-14

申请人： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

发明人： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

IPC分类号： H01L23/525 ,  H01L21/336

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

公开(公告)号：US07084427B2

公开(公告)日：2006-08-01

申请号：US10250175

申请日：2003-06-10

申请人： Patricia Argandona ,  Faisal Azam ,  Andrew Lu ,  Helen Wang

发明人： Patricia Argandona ,  Faisal Azam ,  Andrew Lu ,  Helen Wang

IPC分类号： H01L23/58

CPC分类号： H01L22/34

摘要： The systems and methods enable the determination of the magnitude and direction of overlay of at least two elements in two layers. Overlay measurements along two axes can be obtained using four probe pads and without requiring a decoder. Overlay measurements along a single axis can be obtained using three probe pads and without requiring a decoder. The systems and methods according to this invention require less space and are more time efficient than conventional measurement structures. In the systems and methods of this invention, offsets in a direction are calculated from resistance measurements.

摘要翻译： 这些系统和方法使得能够确定两层中至少两个元素的叠加的大小和方向。 可以使用四个探针焊盘获得两个轴上的叠加测量值，无需解码器。 使用三个探针焊盘可以获得沿着单个轴的覆盖测量，而不需要解码器。 根据本发明的系统和方法需要更少的空间并且比常规测量结构更节约时间。 在本发明的系统和方法中，根据电阻测量计算方向的偏移。

公开(公告)号：US20050019966A1

公开(公告)日：2005-01-27

申请号：US10250175

申请日：2003-06-10

申请人： Patricia Argandona ,  Faisal Azam ,  Andrew Lu ,  Helen Wang

发明人： Patricia Argandona ,  Faisal Azam ,  Andrew Lu ,  Helen Wang

IPC分类号： H01L23/544 ,  G01R31/26

CPC分类号： H01L22/34

摘要： The systems and methods enable the determination of the magnitude and direction of overlay of at least two elements in two layers. Overlay measurements along two axes can be obtained using four probe pads and without requiring a decoder. Overlay measurements along a single axis can be obtained using three probe pads and without requiring a decoder. The systems and methods according to this invention require less space and are more time efficient than conventional measurement structures. In the systems and methods of this invention, offsets in a direction are calculated from resistance measurements.

摘要翻译： 这些系统和方法使得能够确定两层中至少两个元素的叠加的大小和方向。 可以使用四个探针焊盘获得两个轴上的叠加测量值，无需解码器。 使用三个探针焊盘可以获得沿着单个轴的覆盖测量，而不需要解码器。 根据本发明的系统和方法需要更少的空间并且比常规测量结构更节约时间。 在本发明的系统和方法中，根据电阻测量计算方向的偏移。

公开(公告)号：US06372647B1

公开(公告)日：2002-04-16

申请号：US09460870

申请日：1999-12-14

申请人： Andrew Lu ,  Juan Alexander Chediak

发明人： Andrew Lu ,  Juan Alexander Chediak

IPC分类号： H01L21302

CPC分类号： H01L21/76807

摘要： A method of forming a dual damascene pattern in a dielectric, includes etching a pattern of lines minus vias overlapping the lines to a line depth, leaving the dielectric unetched at the via locations; while the vias are etched in a separate step, starting from the top surface of the dielectric and continuing to a via depth greater than the line depth.

摘要翻译： 一种在电介质中形成双镶嵌图案的方法，包括将线的图案与线重叠的线路深度蚀刻到线深度，使得介质在通孔位置处未被蚀刻; 而通孔在单独的步骤中被蚀刻，从电介质的顶表面开始并且继续到大于线深度的通孔深度。

公开(公告)号：US07550303B2

公开(公告)日：2009-06-23

申请号：US11279534

申请日：2006-04-12

申请人： Patricia Argandona ,  Faisal Azam ,  Andrew Lu ,  Helen Wang

发明人： Patricia Argandona ,  Faisal Azam ,  Andrew Lu ,  Helen Wang

IPC分类号： H01L21/66 ,  G06F19/00

CPC分类号： H01L22/34

摘要： Method for measuring misalignment between at least two layers of an integrated circuit. The method includes applying a current between a plurality of probe members in a first layer, wherein a first probe member and a second probe member of the plurality of probe members are substantially aligned along a first axis and partially overlap an overlay target in a second layer, measuring a voltage across the plurality of probe members wherein at least a voltage across the first probe member and a third probe member disposed perpendicular to the first axis and a voltage across the second probe member and the third probe member are measured, and determining an amount of misalignment between the first layer and the second layer along at least one of the first axis and the second axis based on the measuring steps.

摘要翻译： 用于测量集成电路的至少两层之间的未对准的方法。 该方法包括在第一层中的多个探针构件之间施加电流，其中多个探针构件中的第一探针构件和第二探针构件沿着第一轴线基本上对准并且部分地与第二层中的覆盖目标重叠 测量所述多个探针构件上的电压，其中测量所述第一探针构件和垂直于所述第一轴线设置的至少一个电压以及横跨所述第二探针构件和所述第三探针构件的电压，并且确定 基于测量步骤沿着第一轴和第二轴的至少一个，第一层和第二层之间的未对准量。

公开(公告)号：US06924185B2

公开(公告)日：2005-08-02

申请号：US10680618

申请日：2003-10-07

申请人： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

发明人： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

IPC分类号： H01L23/525 ,  H01L21/336

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

摘要翻译： 用于熔丝结构的方法和结构包括绝缘体层，穿过绝缘体层延伸到下面的布线层的多个熔丝电极，连接到电极的电镀熔丝元件和界面壁。 保险丝元件位于绝缘体的外部，并且在绝缘体和保险丝元件之间并置有间隙。 界面壁还包括第一侧壁，第二侧壁和内壁，其中内壁设置在间隙内。 熔丝电极彼此直径相对，并且熔丝元件垂直地设置在熔丝电极的上方。 保险丝元件是电镀，无电镀，或是超薄保险丝。