公开(公告)号：US06924185B2

公开(公告)日：2005-08-02

申请号：US10680618

申请日：2003-10-07

申请人： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

发明人： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

IPC分类号： H01L23/525 ,  H01L21/336

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

摘要翻译： 用于熔丝结构的方法和结构包括绝缘体层，穿过绝缘体层延伸到下面的布线层的多个熔丝电极，连接到电极的电镀熔丝元件和界面壁。 保险丝元件位于绝缘体的外部，并且在绝缘体和保险丝元件之间并置有间隙。 界面壁还包括第一侧壁，第二侧壁和内壁，其中内壁设置在间隙内。 熔丝电极彼此直径相对，并且熔丝元件垂直地设置在熔丝电极的上方。 保险丝元件是电镀，无电镀，或是超薄保险丝。

公开(公告)号：US06927472B2

公开(公告)日：2005-08-09

申请号：US09992344

申请日：2001-11-14

申请人： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

发明人： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

IPC分类号： H01L23/525 ,  H01L21/336

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

公开(公告)号：US06534863B2

公开(公告)日：2003-03-18

申请号：US09781121

申请日：2001-02-09

申请人： George F. Walker ,  Ronald D. Goldblatt ,  Peter A. Gruber ,  Raymond R. Horton ,  Kevin S. Petrarca ,  Richard P. Volant ,  Tien-Jen Cheng

发明人： George F. Walker ,  Ronald D. Goldblatt ,  Peter A. Gruber ,  Raymond R. Horton ,  Kevin S. Petrarca ,  Richard P. Volant ,  Tien-Jen Cheng

IPC分类号： H01L2348

CPC分类号： H01L24/48 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015 ,  H01L2924/00012

摘要： A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

公开(公告)号：US06995475B2

公开(公告)日：2006-02-07

申请号：US10666775

申请日：2003-09-18

申请人： Julie C. Biggs ,  Tien-Jen Cheng ,  David E. Eichstadt ,  Lisa A. Fanti ,  Jonathan H. Griffith ,  Randolph F. Knarr ,  Sarah H. Knickerbocker ,  Kevin S. Petrarca ,  Roger A. Quon ,  Wolfgang Sauter ,  Kamalesh K. Srivastava ,  Richard P. Volant

发明人： Julie C. Biggs ,  Tien-Jen Cheng ,  David E. Eichstadt ,  Lisa A. Fanti ,  Jonathan H. Griffith ,  Randolph F. Knarr ,  Sarah H. Knickerbocker ,  Kevin S. Petrarca ,  Roger A. Quon ,  Wolfgang Sauter ,  Kamalesh K. Srivastava ,  Richard P. Volant

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

摘要翻译： 一种在（I / C）芯片中形成引线键合的方法，包括：提供具有导电焊盘的I / C芯片，所述导电焊盘与覆盖所述焊盘的至少一层电介质材料进行引线接合; 通过暴露所述垫的一部分的电介质材料形成开口。 在衬垫的暴露表面和开口表面上形成至少第一导电层。 在第一导电层上形成种子层; 在种子层上施加光致抗蚀剂; 曝光和显影光致抗蚀剂，其显露出围绕开口的种子层的表面; 去除暴露的种子层; 去除开口中的光致抗蚀剂材料，露出种子层。 在开口中的种子层上电镀至少一层第二导电材料层，以及去除围绕开口的电介质层上的第一导电层。 本发明还包括所得到的结构。

公开(公告)号：US07572726B2

公开(公告)日：2009-08-11

申请号：US11271760

申请日：2005-11-10

申请人： Julie C. Biggs ,  Tien-Jen Cheng ,  David E. Eichstadt ,  Lisa A. Fanti ,  Jonathan H. Griffith ,  Randolph F. Knarr ,  Sarah H. Knickerbocker ,  Kevin S. Petrarca ,  Roger A. Quon ,  Wolfgang Sauter ,  Kamalesh K. Srivastava ,  Richard P. Volant

发明人： Julie C. Biggs ,  Tien-Jen Cheng ,  David E. Eichstadt ,  Lisa A. Fanti ,  Jonathan H. Griffith ,  Randolph F. Knarr ,  Sarah H. Knickerbocker ,  Kevin S. Petrarca ,  Roger A. Quon ,  Wolfgang Sauter ,  Kamalesh K. Srivastava ,  Richard P. Volant

IPC分类号： H01L21/44

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

摘要翻译： 一种在（I / C）芯片中形成引线键合的方法，包括：提供具有导电焊盘的I / C芯片，所述导电焊盘与覆盖所述焊盘的至少一层电介质材料进行引线接合; 通过暴露所述垫的一部分的电介质材料形成开口。 在衬垫的暴露表面和开口表面上形成至少第一导电层。 在第一导电层上形成种子层; 在种子层上施加光致抗蚀剂; 曝光和显影光致抗蚀剂，其显露出围绕开口的种子层的表面; 去除暴露的种子层; 去除开口中的光致抗蚀剂材料，露出种子层。 在开口中的种子层上电镀至少一层第二导电材料层，以及去除围绕开口的电介质层上的第一导电层。 本发明还包括所得到的结构。

公开(公告)号：US09017486B2

公开(公告)日：2015-04-28

申请号：US12878128

申请日：2010-09-09

申请人： Tien-Jen Cheng ,  Zhengwen Li ,  Keith Kwong Hon Wong

发明人： Tien-Jen Cheng ,  Zhengwen Li ,  Keith Kwong Hon Wong

IPC分类号： B08B7/00 ,  B08B7/04 ,  C23C16/44 ,  C23C14/34

CPC分类号： B08B7/04 ,  B08B7/0014 ,  C23C14/34 ,  C23C16/4404

摘要： A method for cleaning a deposition chamber includes forming a deposited layer over an interior surface of the deposition chamber, wherein the deposited layer has a deposited layer stress and a deposited layer modulus; forming a cleaning layer over the deposited layer, wherein a material comprising the cleaning layer is selected such that the cleaning layer adheres to the deposited layer, and has a cleaning layer stress and a cleaning layer modulus, wherein the cleaning layer stress is higher than the deposited layer stress, and wherein the cleaning layer modulus is higher than the deposited layer modulus; and removing the deposited layer and the cleaning layer from the interior of the deposition chamber.

公开(公告)号：US20100038789A1

公开(公告)日：2010-02-18

申请号：US12190906

申请日：2008-08-13

申请人： Tien-Jen Cheng ,  Zhengwen Li ,  Keith Kwong Hon Wong ,  Huilong Zhu

发明人： Tien-Jen Cheng ,  Zhengwen Li ,  Keith Kwong Hon Wong ,  Huilong Zhu

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76868 ,  H01L21/76877 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dielectric layer is patterned with at least one line trough and/or at least one via cavity. A metallic nitride liner is formed on the surfaces of the patterned dielectric layer. A metal liner is formed on the surface of the metallic nitride liner. A conformal copper nitride layer is formed directly on the metal liner by atomic layer deposition (ALD) or chemical vapor deposition (CVD). A Cu seed layer is formed directly on the conformal copper nitride layer. The at least one line trough and/or the at least one via cavity are filled with an electroplated material. The direct contact between the conformal copper nitride layer and the Cu seed layer provides enhanced adhesion strength. The conformal copper nitride layer may be annealed to covert an exposed outer portion into a contiguous Cu layer, which may be employed to reduce the thickness of the Cu seed layer.

摘要翻译： 用至少一个线槽和/或至少一个通孔腔对电介质层进行构图。 金属氮化物衬垫形成在图案化电介质层的表面上。 在金属氮化物衬垫的表面上形成金属衬垫。 通过原子层沉积（ALD）或化学气相沉积（CVD）直接在金属衬垫上形成共形的氮化铜层。 在适形的氮化铜层上直接形成Cu籽晶层。 至少一个线槽和/或至少一个通孔腔被电镀材料填充。 保形氮化铜层和Cu籽晶层之间的直接接触提供了增强的粘合强度。 可以将共形的氮化铜层退火以将暴露的外部部分翻转成连续的Cu层，其可用于减小Cu籽晶层的厚度。

公开(公告)号：US07566649B2

公开(公告)日：2009-07-28

申请号：US11858147

申请日：2007-09-20

申请人： William E. Bernier ,  Tien-Jen Cheng ,  Marie S. Cole ,  David E. Eichstadt ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Lewis S. Goldmann ,  John U. Knickerbocker ,  Tasha E. Lopez ,  David J. Welsh

发明人： William E. Bernier ,  Tien-Jen Cheng ,  Marie S. Cole ,  David E. Eichstadt ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Lewis S. Goldmann ,  John U. Knickerbocker ,  Tasha E. Lopez ,  David J. Welsh

IPC分类号： H01L21/44 ,  H01L21/50 ,  H01L21/48 ,  H01L23/52 ,  H01L23/48 ,  H01L23/485 ,  H01L23/488

CPC分类号： H01L21/563 ,  H01L23/3171 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13566 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01R43/0256 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0133 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/0401

摘要： Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.

摘要翻译： 公开了一种形成集成电路结构的方法，其在器件上形成无铅连接器，用可压缩膜围绕无铅连接器，将器件连接到载体（无铅连接器将器件电连接到载体上 ），并用绝缘底部填充物填充载体和装置之间的间隙。

公开(公告)号：US20060009022A1

公开(公告)日：2006-01-12

申请号：US11162468

申请日：2005-09-12

申请人： Kamalesh Srivastava ,  Subhash Shinde ,  Tien-Jen Cheng ,  Sarah Knickerbocker ,  Roger Quon ,  William Sablinski ,  Julie Biggs ,  David Eichstadt ,  Jonathan Griffith

发明人： Kamalesh Srivastava ,  Subhash Shinde ,  Tien-Jen Cheng ,  Sarah Knickerbocker ,  Roger Quon ,  William Sablinski ,  Julie Biggs ,  David Eichstadt ,  Jonathan Griffith

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014

摘要： A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.

摘要翻译： 用于形成半导体器件的互连结构的方法包括在钝化层中限定通孔，以暴露半导体器件中的顶部金属层。 在钝化层，通孔的侧壁和顶部金属层上形成种子层。 在种子层的暴露部分上形成阻挡层，暴露部分由第一图案化开口限定。 半导体器件被退火以使来自阻挡层的原子扩散到其中的晶种层中，其中退火使种子层的扩散区域相对于种子层的未扩散区域具有改变的电阻率和电极电位 。

公开(公告)号：US20050245070A1

公开(公告)日：2005-11-03

申请号：US10709321

申请日：2004-04-28

申请人： Panayotis Andricacos ,  Tien-Jen Cheng ,  Emanuel Cooper ,  David Eichstadt ,  Jonathan Griffith ,  Randolph Knarr ,  Roger Quon ,  Erik Roggeman

发明人： Panayotis Andricacos ,  Tien-Jen Cheng ,  Emanuel Cooper ,  David Eichstadt ,  Jonathan Griffith ,  Randolph Knarr ,  Roger Quon ,  Erik Roggeman

IPC分类号： H01L21/288 ,  H01L21/4763 ,  H01L21/60 ,  H01L23/485

CPC分类号： H01L21/2885 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/01028 ,  H01L2924/00014

摘要： A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.

摘要翻译： 公开了一种创建用于互连中的多层屏障的方法，用于互连的屏障和包括屏障的互连的方法。 该方法包括通过使用单个电镀化学品在器件端子的凹部中产生多层屏障，以增强由于铜的扩散而导致的排除和去层压的保护，无论是通过自扩散还是电迁移。 屏障包括至少第一层富镍材料和第二层富铜材料。 阻挡层可以为高级互补金属氧化物半导体（CMOS）设计使用更高的电流密度，并扩展电流CMOS设计的可靠性，无论焊料选择如何。 而且，该技术很容易适用于电镀互连如C4的制造方法。