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42 条记录 (耗时 0.051 秒)

    Diaphragm activated micro-electromechanical switch
    5.
    发明授权
    Diaphragm activated micro-electromechanical switch 有权
    隔膜激活微机电开关

    公开(公告)号：US07256670B2

    公开(公告)日：2007-08-14

    申请号：US10523310

    申请日：2002-08-26

    申请人： Christopher V. Jahnes ,  Jennifer L. Lund ,  Katherine L. Saenger ,  Richard P. Volant

    发明人： Christopher V. Jahnes ,  Jennifer L. Lund ,  Katherine L. Saenger ,  Richard P. Volant

    IPC分类号： H01H51/22

    CPC分类号： H01H59/0009

    摘要： A micro-electromechanical (MEM) RF switch provided with a deflectable membrane (60) activates a switch contact or plunger (40). The membrane incorporates interdigitated metal electrodes (70) which cause a stress gradient in the membrane when activated by way of a DC electric field. The stress gradient results in a predictable bending or displacement of the membrane (60), and is used to mechanically displace the switch contact (30). An RF gap area (25) located within the cavity (250) is totally segregated from the gaps (71) between the interdigitated metal electrodes (70). The membrane is electrostatically displaced in two opposing directions, thereby aiding to activate and deactivate the switch. The micro-electromechanical switch includes: a cavity (250); at least one conductive path (20) integral to a first surface bordering the cavity; a flexible membrane (60) parallel to the first surface bordering the cavity (250), the flexible membrane (60) having a plurality of actuating electrodes (70); and a plunger (40) attached to the flexible membrane (60) in a direction away from the actuating electrodes (70), the plunger (40) having a conductive surface that makes electric contact with the conductive paths, opening and closing the switch.

    摘要翻译： 设置有可偏转膜（60）的微机电（MEM）RF开关激活开关触点或柱塞（40）。 膜包含交叉指向的金属电极（70），其通过DC电场激活时引起膜中的应力梯度。 应力梯度导致膜（60）的可预测的弯曲或位移，并且用于机械地移动开关触点（30）。 位于空腔（250）内的RF间隙区域（25）与交叉指向的金属电极（70）之间的间隙（71）完全分离。 膜在两个相反的方向上静电位移，从而有助于启动和停用开关。 微机电开关包括：空腔（250）; 至少一个导电通路（20），与所述空腔相邻的第一表面成一体; 柔性膜（60），其平行于与所述腔（250）接壤的所述第一表面，所述柔性膜（60）具有多个致动电极（70）; 以及沿远离所述致动电极（70）的方向附接到所述柔性膜（60）的柱塞（40），所述柱塞（40）具有导电表面，所述导电表面与所述导电路径电接触，所述开关闭合。

    Damascene anti-fuse with slot via
    6.
    发明授权
    Damascene anti-fuse with slot via 失效
    大马士革防熔丝与插槽通孔

    公开(公告)号：US06380003B1

    公开(公告)日：2002-04-30

    申请号：US09469374

    申请日：1999-12-22

    申请人： Christopher V. Jahnes ,  Chandrasekhar Narayan ,  Carl J. Radens

    发明人： Christopher V. Jahnes ,  Chandrasekhar Narayan ,  Carl J. Radens

    IPC分类号： H01L2182

    CPC分类号： H01L23/5252 ,  H01L21/76816 ,  H01L2221/1057 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Interconnect structures comprising a substrate having a first level of electrically conductive features formed thereon; a patterned interlevel dielectric material formed on said substrate, wherein said patterned interlevel dielectric includes via spaces, wherein at least one of said via spaces is a slot via in which an anti-fuse material is formed on a portion thereof; and a second level of electrically conductive features formed in said spaces, whereby the anti-fuse material in the slot via provides a connection between the first and second levels of electrically conductive features and a method of fabricating the same.

    摘要翻译： 互连结构，包括其上形成有第一层导电特征的基底; 形成在所述衬底上的图案化层间电介质材料，其中所述图案化层间电介质包括通孔空间，其中所述通孔空间中的至少一个是其中在其一部分上形成反熔丝材料的槽通孔; 以及形成在所述空间中的第二级别的导电特征，由此所述槽通孔中的所述反熔丝材料提供所述第一和第二层导电特征之间的连接及其制造方法。

    Protective hardmask for producing interconnect structures
    7.
    发明授权
    Protective hardmask for producing interconnect structures 失效
    用于生产互连结构的保护硬掩模

    公开(公告)号：US06720249B1

    公开(公告)日：2004-04-13

    申请号：US09550943

    申请日：2000-04-17

    申请人： Timothy J. Dalton ,  Christopher V. Jahnes ,  Joyce C. Liu ,  Sampath Purushothaman

    发明人： Timothy J. Dalton ,  Christopher V. Jahnes ,  Joyce C. Liu ,  Sampath Purushothaman

    IPC分类号： H01L214763

    CPC分类号： H01L21/76835 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a permanent protective hardmask which protects the dielectric properties of a main dielectric layer having a desirably low dielectric constant in a semiconductor device from undesirable increases in the dielectric constant, undesirable increases in current leakage, and low device yield from surface scratching during subsequent processing steps. The protective hardmask further includes a single layer or dual layer sacrificial hardmask particularly useful when interconnect structures such as via openings and/or lines are formed in the low dielectric material during the course of making the final product. The sacrificial hardmask layers and the permanent hardmask layer may be formed in a single step from a same precursor wherein process conditions are altered to provide films of differing dielectric constants. Most preferably, a dual damascene structure has a tri-layer hardmask comprising silicon carbide BLoK™, PECVD silicon nitride, and PECVD silicon dioxide, respectively, formed over a bulk low dielectric constant interlevel dielectric prior to forming the interconnect structures in the interlevel dielectric.

    摘要翻译： 本发明提供一种永久性保护性硬掩模，其保护半导体器件中具有期望的低介电常数的主电介质层的介电性能，不需要介电常数的增加，不期望的电流泄漏增加，以及在表面划伤期间的低的器件产量 后续处理步骤。 保护性硬掩模还包括单层或双层牺牲硬掩模，在制造最终产品的过程中，在低电介质材料中形成诸如通孔开口和/或线之间的互连结构时尤其有用。 牺牲硬掩模层和永久硬掩模层可以从相同的前体在单个步骤中形成，其中改变工艺条件以提供不同介电常数的膜。 最优选地，双镶嵌结构具有三层硬掩模，其在形成层间的互连结构之前分别形成在体低介电常数层间电介质上的碳化硅BLoK TM，PECVD氮化硅和PECVD二氧化硅 电介质。