公开(公告)号：US06924185B2

公开(公告)日：2005-08-02

申请号：US10680618

申请日：2003-10-07

申请人： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

发明人： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

IPC分类号： H01L23/525 ,  H01L21/336

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

摘要翻译： 用于熔丝结构的方法和结构包括绝缘体层，穿过绝缘体层延伸到下面的布线层的多个熔丝电极，连接到电极的电镀熔丝元件和界面壁。 保险丝元件位于绝缘体的外部，并且在绝缘体和保险丝元件之间并置有间隙。 界面壁还包括第一侧壁，第二侧壁和内壁，其中内壁设置在间隙内。 熔丝电极彼此直径相对，并且熔丝元件垂直地设置在熔丝电极的上方。 保险丝元件是电镀，无电镀，或是超薄保险丝。

公开(公告)号：US06927472B2

公开(公告)日：2005-08-09

申请号：US09992344

申请日：2001-11-14

申请人： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

发明人： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

IPC分类号： H01L23/525 ,  H01L21/336

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

公开(公告)号：US06534863B2

公开(公告)日：2003-03-18

申请号：US09781121

申请日：2001-02-09

申请人： George F. Walker ,  Ronald D. Goldblatt ,  Peter A. Gruber ,  Raymond R. Horton ,  Kevin S. Petrarca ,  Richard P. Volant ,  Tien-Jen Cheng

发明人： George F. Walker ,  Ronald D. Goldblatt ,  Peter A. Gruber ,  Raymond R. Horton ,  Kevin S. Petrarca ,  Richard P. Volant ,  Tien-Jen Cheng

IPC分类号： H01L2348

CPC分类号： H01L24/48 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015 ,  H01L2924/00012

摘要： A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

公开(公告)号：US07355271B2

公开(公告)日：2008-04-08

申请号：US10573561

申请日：2003-09-30

申请人： Richard P. Volant ,  Kevin S. Petrarca ,  George F. Walker

发明人： Richard P. Volant ,  Kevin S. Petrarca ,  George F. Walker

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5387 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/9222 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2225/06589 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00

摘要： A three-dimensional package consisting of a plurality of folded integrated circuit chips (100, 110, 120) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip (130) is provided with additional interconnect wiring to a substrate (500), package or printed circuit board. Further described, is a method of providing a flexible arrangement of interconnected chips that are folded over into a three-dimensional arrangements to consume less aerial space when mounted on a substrate, second-level package or printed circuit board.

摘要翻译： 描述了由多个折叠集成电路芯片（100,110,120）组成的三维封装，其中至少一个芯片提供用于与堆叠的附加芯片的电连接的互连路径，并且至少一个芯片（130）是 提供与衬底（500），封装或印刷电路板的附加互连布线。 进一步描述的是提供互连芯片的柔性布置的方法，其被折叠成三维布置以在安装在基板，二级封装或印刷电路板上时消耗较少的空中空间。

公开(公告)号：US07273806B2

公开(公告)日：2007-09-25

申请号：US10905013

申请日：2004-12-09

申请人： Robert A. Groves ,  Peter A. Gruber ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

发明人： Robert A. Groves ,  Peter A. Gruber ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

IPC分类号： H01L21/44

CPC分类号： H05K3/3468 ,  G01R1/07314 ,  G01R3/00 ,  H01L21/4853 ,  H01L21/6835 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01058 ,  H01L2924/01066 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H05K3/325 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/128 ,  H05K2203/162 ,  H05K2203/167 ,  H01L2224/0401

摘要： Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on a conventional semiconductor substrate after the typical BEOL, and prior to packaging. The method may provide better electromigration characteristics, lower resistivity, and higher Q factors for conductive structures. In addition, the method is backwardly compatible and customizable.

摘要翻译： 公开了在封装之前在基板上形成导电结构的方法和根据该方法生成的测试探针结构。 导电结构包括通过注射成型的焊料形成的高纵横比结构。 本发明可以应用于在典型的BEOL之后以及在封装之前在常规半导体衬底上形成无源元件和互连。 该方法可以为导电结构提供更好的电迁移特性，较低的电阻率和更高的Q因子。 此外，该方法可以向后兼容并可定制。

公开(公告)号：US06339024B1

公开(公告)日：2002-01-15

申请号：US09605728

申请日：2000-06-28

申请人： Kevin S. Petrarca ,  John E. Heidenreich, III ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  Richard P. Volant ,  George F. Walker

发明人： Kevin S. Petrarca ,  John E. Heidenreich, III ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  Richard P. Volant ,  George F. Walker

IPC分类号： H01L2044

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14

摘要： A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 &mgr;m. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.

摘要翻译： 一种制造集成电路的方法，其中提供具有大于或等于1.5μm厚度的集成电路的最上半导体层中的导电结构。 导电结构的厚度足够大，以有效地保护最高半导体层下面的任何层免受来自压力（例如由测试探针施加的压力）的损害。 在优选的实施方案中，传统的铝TD匀染被丢弃，有利于沉积在增厚的导电层上的金。

公开(公告)号：US20120286236A1

公开(公告)日：2012-11-15

申请号：US13555383

申请日：2012-07-23

申请人： Harold J. HOVEL ,  Qiang Huang ,  Xiaoyan Shao ,  James Vichiconti ,  George F. Walker

发明人： Harold J. HOVEL ,  Qiang Huang ,  Xiaoyan Shao ,  James Vichiconti ,  George F. Walker

IPC分类号： H01L29/06 ,  B82Y99/00

CPC分类号： H01L31/18 ,  B82Y10/00 ,  B82Y30/00 ,  C30B29/02 ,  C30B29/06 ,  C30B29/40 ,  C30B29/52 ,  C30B29/60 ,  C30B29/605 ,  C30B33/10 ,  H01L21/30604 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L31/0352 ,  H01L33/20

摘要： Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.

摘要翻译： 在没有模板的情况下通过从两种或更多种半导体材料的层状结构中去除材料来制造分段半导体纳​​米线。 去除在层状结构的表面上的某些位置处发生，并且优选地沿着结晶轴的方向延伸，使得具有分段结构的纳米线保持在很少或不发生去除的位置。 不同片段之间的界面可以垂直于纳米线的纵向方向或与之相垂直。

公开(公告)号：US20120193231A1

公开(公告)日：2012-08-02

申请号：US13359750

申请日：2012-01-27

申请人： Ali Afzali-Ardakani ,  Stefan Harrer ,  Binquan Luan ,  Glenn J. Martyna ,  Hongbo Peng ,  Stephen M. Rossnagel ,  Gustavo A. Stolovitzky ,  Philip S. Waggoner ,  George F. Walker

发明人： Ali Afzali-Ardakani ,  Stefan Harrer ,  Binquan Luan ,  Glenn J. Martyna ,  Hongbo Peng ,  Stephen M. Rossnagel ,  Gustavo A. Stolovitzky ,  Philip S. Waggoner ,  George F. Walker

IPC分类号： G01N27/447 ,  G01N27/453

CPC分类号： G01N33/48721 ,  C12Q1/6869 ,  C12Q2563/116 ,  C12Q2563/157 ,  C12Q2565/607 ,  C12Q2565/631

摘要： A nanodevice is provided. A reservoir is filled with an ionic fluid. A membrane separates the reservoir, and the membrane includes electrode layers separated by insulating layers in which the electrode layers have an organic coating. A nanopore is formed through the membrane, and the organic coating on the electrode layers forms transient bonds to a base of a molecule in the nanopore. When a first voltage is applied to the electrode layers a tunneling current is generated by the base in the nanopore, and the tunneling current travels through the transient bonds formed to the base to be measured as a current signature for distinguishing the base.

摘要翻译： 提供了一个纳米设备。 储存器充满离子流体。 膜分离储存器，并且膜包括由绝缘层分离的电极层，其中电极层具有有机涂层。 通过膜形成纳米孔，并且电极层上的有机涂层与纳米孔中分子的碱基形成瞬态键。 当第一电压施加到电极层时，通过纳米孔中的基底产生隧道电流，并且隧道电流通过形成到待测量的基极的瞬态键作为用于区分基极的电流签名传播。

公开(公告)号：US5635846A

公开(公告)日：1997-06-03

申请号：US55485

申请日：1993-04-30

申请人： Brian S. Beaman ,  Keith E. Fogel ,  Paul A. Lauro ,  Maurice H. Norcott ,  Da-Yuan Shih ,  George F. Walker

发明人： Brian S. Beaman ,  Keith E. Fogel ,  Paul A. Lauro ,  Maurice H. Norcott ,  Da-Yuan Shih ,  George F. Walker

IPC分类号： H01L23/52 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  G01R31/02

CPC分类号： G01R1/07371 ,  G01R1/07307 ,  G01R1/07314 ,  G01R1/07342 ,  G01R3/00 ,  G01R31/2886 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/0652 ,  G01R1/06711 ,  G01R1/0675 ,  G01R1/07378 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/78301 ,  H01L2224/85205 ,  H01L2224/85214 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/1627 ,  H01L2924/19107 ,  H01L2924/3011 ,  Y10S29/029 ,  Y10T29/49004 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49158 ,  Y10T29/49162 ,  Y10T29/49192 ,  Y10T29/53174

摘要： A high density test probe is for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.

摘要翻译： 高密度测试探头用于测试晶圆形式的高密度和高性能集成电路或分立芯片。 测试探针由嵌入柔性或高模量弹性体材料的细长电导体的密集阵列形成。 使用陶瓷集成电路芯片封装基板等标准封装基板来提供空间变压器。 电线被连接到空间变压器表面上的接触焊盘阵列。 空间变压器由多层集成电路芯片封装基板形成。 电线与接触位置阵列一样密集。 围绕着向外突出的线的阵列设置模具。 液体弹性体设置在模具中以填充电线之间的空间。 弹性体被固化并且模具被去除，留下布置在弹性体中并且与空间变压器电接触的线阵列。空间变压器可以具有一组引脚，这些引脚位于空间变压器的相反表面上， 其中细长导体被接合。 这些销插入第二空间变压器（例如印刷电路板）上的插座中以形成探针组件。 或者，插入器电连接器可以设置在第一和第二空间变压器之间。

公开(公告)号：US5593720A

公开(公告)日：1997-01-14

申请号：US447564

申请日：1995-05-23

申请人： Kie Y. Ahn ,  James L. Hedrick, Jr. ,  Jeffrey W. Labadie ,  Kang-Wook Lee ,  Robert J. Twieg ,  Alfred Viehbeck ,  George F. Walker

发明人： Kie Y. Ahn ,  James L. Hedrick, Jr. ,  Jeffrey W. Labadie ,  Kang-Wook Lee ,  Robert J. Twieg ,  Alfred Viehbeck ,  George F. Walker

IPC分类号： C08G73/18 ,  C08L71/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L23/532 ,  H05K1/00 ,  H05K1/03 ,  B05D5/12

CPC分类号： H01L23/5329 ,  C08G73/18 ,  C08L71/00 ,  H01L23/293 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0346 ,  H05K3/4676 ,  Y10S428/901 ,  Y10T29/49155 ,  Y10T29/49171 ,  Y10T428/24917 ,  Y10T428/31605 ,  Y10T428/31721

摘要： A multilevel electronic package comprising at least two levels, each level including a poly(aryl ether benzimidazole), a polymide and copper. A process of preparing this package is disclosed. Several novel poly(aryl ether benzimidazoles) useful in preparing this package are also set forth.

摘要翻译： 包括至少两个级别的多级电子封装，每个级别包括聚（芳基醚苯并咪唑），聚酰亚胺和铜。 公开了制备该包装的过程。 还介绍了可用于制备该包装的几种新颖的聚（芳基醚苯并咪唑）。