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    GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPROACH TO TARGET CD FOR SELECTED TRANSISTORS
    1.
    发明申请
    GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPROACH TO TARGET CD FOR SELECTED TRANSISTORS 有权
    使用蚀刻或干蚀刻方法对选定的晶体管的目标光盘进行栅格扫描过程

    公开(公告)号：US20120032308A1

    公开(公告)日：2012-02-09

    申请号：US13278343

    申请日：2011-10-21

    申请人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

    发明人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

    IPC分类号： H01L21/306 ,  H01L29/06

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/823456

    摘要： Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

    摘要翻译： 公开了用于在半导体器件中靶向所选晶体管的CD的方法和装置。 通过在硬掩模层中形成具有不同量的与其相关联的间隔物材料的硬掩模线来完成不同的CD。 对应于所选择的晶体管的硬掩模线被被涂覆在硬掩模层上的抗蚀剂覆盖或未覆盖。 然后，从硬掩模线选择性地去除间隔物材料以改变硬掩模线和相关联的侧壁间隔物的宽度。 然后通过硬掩模线中的空间蚀刻栅极层以形成具有不同宽度的栅极线和目标CD。

    Gate trim process using either wet etch or dry etch approach to target CD for selected transistors
    2.
    发明授权
    Gate trim process using either wet etch or dry etch approach to target CD for selected transistors 有权
    使用湿蚀刻或干法蚀刻方法对所选晶体管靶CD进行栅极修整处理

    公开(公告)号：US08067314B2

    公开(公告)日：2011-11-29

    申请号：US12424023

    申请日：2009-04-15

    申请人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

    发明人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

    IPC分类号： H01L21/76

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/823456

    摘要： Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

    摘要翻译： 公开了用于在半导体器件中靶向所选晶体管的CD的方法和装置。 通过在硬掩模层中形成具有不同量的与其相关联的间隔物材料的硬掩模线来完成不同的CD。 对应于所选择的晶体管的硬掩模线被被涂覆在硬掩模层上的抗蚀剂覆盖或未覆盖。 然后，从硬掩模线选择性地去除间隔物材料以改变硬掩模线和相关联的侧壁间隔物的宽度。 然后通过硬掩模线中的空间蚀刻栅极层以形成具有不同宽度的栅极线和目标CD。

    Memory device etch methods
    3.
    发明授权
    Memory device etch methods 有权
    存储器件蚀刻方法

    公开(公告)号：US07972951B2

    公开(公告)日：2011-07-05

    申请号：US12688477

    申请日：2010-01-15

    申请人： Angela T. Hui ,  Jihwan Choi

    发明人： Angela T. Hui ,  Jihwan Choi

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32137 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568

    摘要： A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF4) and trifluoromethane (CHF3) to etch at least the control gate layer.

    摘要翻译： 一种制造存储器件的方法在衬底上形成第一介电层，在第一介电层之上形成电荷存储层，在电荷存储层上形成第二介电层，并在第二介电层上形成控制栅极层。 该方法还在控制栅极层上形成硬掩模层，在硬掩模层上形成底部抗反射涂层（BARC）层，并提供包括四氟甲烷（CF4）和三氟甲烷（CHF 3）在内的蚀刻化学品，以蚀刻 至少控制门层。

    GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPRAOCH TO TARGET CD FOR SELECTED TRANSISTORS
    4.
    发明申请
    GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPRAOCH TO TARGET CD FOR SELECTED TRANSISTORS 有权
    使用蚀刻蚀刻或干蚀刻蚀刻技术的GATE TRIM工艺可用于所选晶体管的目标光盘

    公开(公告)号：US20100264519A1

    公开(公告)日：2010-10-21

    申请号：US12424023

    申请日：2009-04-15

    申请人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

    发明人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

    IPC分类号： H01L29/423 ,  H01L21/306

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/823456

    摘要： Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

    摘要翻译： 公开了用于在半导体器件中靶向所选晶体管的CD的方法和装置。 通过在硬掩模层中形成具有不同量的与其相关联的间隔物材料的硬掩模线来完成不同的CD。 对应于所选择的晶体管的硬掩模线被被涂覆在硬掩模层上的抗蚀剂覆盖或未覆盖。 然后，从硬掩模线选择性地去除间隔物材料以改变硬掩模线和相关联的侧壁间隔物的宽度。 然后通过硬掩模线中的空间蚀刻栅极层以形成具有不同宽度的栅极线和目标CD。

    Memory device etch methods
    5.
    发明授权
    Memory device etch methods 有权
    存储器件蚀刻方法

    公开(公告)号：US07670959B2

    公开(公告)日：2010-03-02

    申请号：US11616085

    申请日：2006-12-26

    申请人： Angela T. Hui ,  Jihwan Choi

    发明人： Angela T. Hui ,  Jihwan Choi

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32137 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568

    摘要： A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF4) and trifluoromethane (CHF3) to etch at least the control gate layer.

    摘要翻译： 一种制造存储器件的方法在衬底上形成第一介电层，在第一介电层之上形成电荷存储层，在电荷存储层上形成第二介电层，并在第二介电层上形成控制栅极层。 该方法还在控制栅极层上形成硬掩模层，在硬掩模层上形成底部抗反射涂层（BARC）层，并提供包括四氟甲烷（CF4）和三氟甲烷（CHF 3）在内的蚀刻化学品，以蚀刻 至少控制门层。

    Gate trim process using either wet etch or dry etch approach to target CD for selected transistors
    6.
    发明授权
    Gate trim process using either wet etch or dry etch approach to target CD for selected transistors 有权
    使用湿蚀刻或干法蚀刻方法对所选晶体管靶CD进行栅极修整处理

    公开(公告)号：US08409994B2

    公开(公告)日：2013-04-02

    申请号：US13278343

    申请日：2011-10-21

    申请人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

    发明人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/823456

    摘要： Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

    摘要翻译： 公开了用于在半导体器件中靶向所选晶体管的CD的方法和装置。 通过在硬掩模层中形成具有不同量的与其相关联的间隔物材料的硬掩模线来完成不同的CD。 对应于所选择的晶体管的硬掩模线被被涂覆在硬掩模层上的抗蚀剂覆盖或未覆盖。 然后，从硬掩模线选择性地去除间隔物材料以改变硬掩模线和相关联的侧壁间隔物的宽度。 然后通过硬掩模线中的空间蚀刻栅极层以形成具有不同宽度的栅极线和目标CD。

    MEMORY DEVICE ETCH METHODS
    7.
    发明申请
    MEMORY DEVICE ETCH METHODS 有权
    存储器件蚀刻方法

    公开(公告)号：US20080153298A1

    公开(公告)日：2008-06-26

    申请号：US11616085

    申请日：2006-12-26

    申请人： Angela T. Hui ,  Jihwan Choi

    发明人： Angela T. Hui ,  Jihwan Choi

    IPC分类号： H01L21/311

    CPC分类号： H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32137 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568

    摘要： A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF4) and trifluoromethane (CHF3) to etch at least the control gate layer.

    摘要翻译： 一种制造存储器件的方法在衬底上形成第一介电层，在第一介电层之上形成电荷存储层，在电荷存储层上形成第二介电层，并在第二介电层上形成控制栅极层。 该方法还在控制栅极层上形成硬掩模层，在硬掩模层之上形成底部抗反射涂层（BARC）层，并提供包括四氟甲烷（CF 4 N） 和三氟甲烷（CHF 3 N 3），以至少蚀刻控制栅极层。

    HTO offset for long Leffective, better device performance
    8.
    发明授权
    HTO offset for long Leffective, better device performance 有权
    HTO偏移长期有效，设备性能更好

    公开(公告)号：US08653581B2

    公开(公告)日：2014-02-18

    申请号：US12342016

    申请日：2008-12-22

    申请人： Ning Cheng ,  Huaqiang Wu ,  Hiro Kinoshita ,  Jihwan Choi ,  Angela Hui

    发明人： Ning Cheng ,  Huaqiang Wu ,  Hiro Kinoshita ,  Jihwan Choi ,  Angela Hui

    IPC分类号： H01L27/115

    CPC分类号： H01L29/792 ,  G11C16/3427 ,  H01L21/26586 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/1083 ,  H01L29/66833 ,  H01L29/7923

    摘要： Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

    摘要翻译： 提供具有增加的有效信道长度和/或改善的TPD特性的存储器件，以及制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。 存储单元包含电荷捕获介质堆叠，多晶硅栅极，一对凹穴注入区域和一对位线。 位线可以通过在较高能级和/或较高浓度的掺杂剂的注入工艺形成，而不会受到器件短沟道卷绕问题的影响，因为位线侧壁处的间隔物在较窄的植入区域中约束植入物。

    HTO offset and BL trench process for memory device to improve device performance
    9.
    发明授权
    HTO offset and BL trench process for memory device to improve device performance 有权
    HTO偏移和BL沟槽工艺为存储器件提高器件性能

    公开(公告)号：US08330209B2

    公开(公告)日：2012-12-11

    申请号：US13069710

    申请日：2011-03-23

    申请人： Ning Cheng ,  Huaqiang Wu ,  Hiro Kinoshita ,  Jihwan Choi

    发明人： Ning Cheng ,  Huaqiang Wu ,  Hiro Kinoshita ,  Jihwan Choi

    IPC分类号： H01L29/792

    CPC分类号： H01L29/66833 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/7923

    摘要： Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

    摘要翻译： 提供具有增加的有效信道长度和/或改善的TPD特性的存储器件，以及制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。 位线电介质可以延伸到半导体中。 存储单元包含电荷捕获介质堆叠，多晶硅栅极，一对凹穴注入区域和一对位线。 位线可以通过在较高能级和/或较高浓度的掺杂剂的注入工艺形成，而不会受到器件短沟道卷绕问题的影响，因为位线侧壁处的间隔物在较窄的植入区域中约束植入物。