摘要:
A method of forming a plurality of contact holes of varying pitch and density in a contact layer of an integrated circuit device is provided. The plurality of contact holes can include a plurality of regularly spaced contact holes having a first pitch along a first direction and a plurality of semi-isolated contact holes having a second pitch along a second direction. A double-dipole illumination source can transmit light energy through a mask having a pattern corresponding to a desired contact hole pattern. The double-dipole illumination source can include a first dipole aperture, which is oriented and optimized for patterning the regularly spaced contact holes, and a second dipole aperture, which is oriented substantially orthogonal to the first dipole aperture and optimized for patterning the plurality of semi-isolated contact holes. The contact layer can be etched using the patterned photoresist layer.
摘要:
A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要:
A method of producing design rules including generating a plurality of parametrically varying geometric layouts and simulating how each geometric layout will pattern on a wafer. Edges of structures within the simulated geometric layouts can be classified based on manufacturability and design rules can be created to disallow layouts demonstrating poor manufacturability.
摘要:
A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.
摘要:
A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要:
A method includes providing an initial IC device design, which design has a desired set of electrical characteristics. A layout representation corresponding to the initial device design is generated. A simulation tool is used to determine whether the layout representation corresponds to an IC device design having the desired electrical characteristics. In addition, the variation between structures within IC device designed due to process variations is evaluated using the simulation tool. This variation can be used to determine whether the design is optimized.
摘要:
A method of fabricating a semiconductor device using lithography. The method can include providing a wafer assembly having a layer to be processed disposed under a photo resist layer and illuminating the wafer assembly with an exposure dose transmitted through a birefringent material disposed between a final optical element of an imaging subsystem used to transmit the exposure dose and the photo resist layer. Also disclosed is a wafer assembly from which at least one semiconductor device can be fabricated. The wafer assembly can include a layer to be processed, a photo resist layer disposed over the layer to be processed and a contrast enhancing, birefringent top anti-reflecting coating (TARC).
摘要:
A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.
摘要:
A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposited carbon film to form spacers on lateral side walls of the aperture of the patterned photoresist layer, etching the substrate using the formed spacers and patterned photoresist layer as a pattern to form a trench having a second width, and removing the patterned photoresist layer and formed spacers using an oxidizing etch.
摘要:
A method of operating an immersion lithography system, including steps of immersing at least a portion of a wafer to be exposed in an immersion medium, wherein the immersion medium comprises at least one bubble; directing an ultrasonic wave through at least a portion of the immersion medium to disrupt and/or dissipate the at least one bubble; and exposing the wafer with an exposure pattern by passing electromagnetic radiation through the immersion medium subsequent to the directing. Also disclosed is a monitoring and control system for an immersion lithography system.