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公开(公告)号：US10554207B1
公开(公告)日：2020-02-04
申请号：US16051058
申请日：2018-07-31
申请人： Anna Y. Herr , Quentin P. Herr , Ryan Edward Clarke , Harold Clifton Hearne, III , Alexander Louis Braun , Randall M. Burnett , Timothy Chi-Chao Lee
发明人： Anna Y. Herr , Quentin P. Herr , Ryan Edward Clarke , Harold Clifton Hearne, III , Alexander Louis Braun , Randall M. Burnett , Timothy Chi-Chao Lee
IPC分类号： H03K19/195 , H03K3/38 , G11C11/44 , G06N10/00
摘要： Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.
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公开(公告)号：US11159168B2
公开(公告)日：2021-10-26
申请号：US17094452
申请日：2020-11-10
申请人： Anna Y. Herr , Quentin P. Herr , Ryan Edward Clarke , Harold Clifton Hearne, III , Alexander Louis Braun , Randall M. Burnett , Timothy Chi-Chao Lee
发明人： Anna Y. Herr , Quentin P. Herr , Ryan Edward Clarke , Harold Clifton Hearne, III , Alexander Louis Braun , Randall M. Burnett , Timothy Chi-Chao Lee
IPC分类号： H03K19/195 , G06N10/00 , G11C11/44 , H03K3/38
摘要： Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.
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公开(公告)号：US09876505B1
公开(公告)日：2018-01-23
申请号：US15256213
申请日：2016-09-02
IPC分类号： H03K19/195 , G06N99/00 , H04B1/40
CPC分类号： H03K19/195 , G06N99/002 , H03K3/38 , H03K19/1952 , H04B1/40
摘要： An isochronous receiver system is provided and includes a single flux quantum (SFQ) receiver to receive a data signal from a transmission line. The single flux quantum receiver then converts the data signal to an SFQ signal. The system also includes a converter system to convert the SFQ signal to a reciprocal quantum logic (RQL) signal and to phase-align the RQL signal with a sampling phase of an AC clock signal.
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公开(公告)号：US10102902B2
公开(公告)日：2018-10-16
申请号：US15714698
申请日：2017-09-25
IPC分类号： G11C11/44 , H03K3/38 , H03K19/195
摘要： One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single flux quantum (SFQ) pulse provided on a write enable input and a respective presence of or absence of a write data SFQ pulse provided on a data write input. The circuit also includes a storage loop coupled to the Josephson D-gate. The storage loop can be configured to store the digital state and to readout the digital state at an output in response to a read enable SFQ pulse provided on a read enable input and a read data SFQ pulse provided on a read data input.
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公开(公告)号：US09812192B1
公开(公告)日：2017-11-07
申请号：US15351065
申请日：2016-11-14
IPC分类号： G11C11/44
CPC分类号： G11C11/44 , H03K3/38 , H03K19/195
摘要： One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single flux quantum (SFQ) pulse provided on a write enable input and a respective presence of or absence of a write data SFQ pulse provided on a data write input. The circuit also includes a storage loop coupled to the Josephson D-gate. The storage loop can be configured to store the digital state and to readout the digital state at an output in response to a read enable SFQ pulse provided on a read enable input and a read data SFQ pulse provided on a read data input.
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公开(公告)号：US10587245B1
公开(公告)日：2020-03-10
申请号：US16188730
申请日：2018-11-13
IPC分类号： H01L39/02 , H03K3/012 , H03H7/01 , H03K17/92 , H03K19/195
摘要： One example includes a superconducting transmission line driver system. The system includes an input stage configured to receive an input pulse and an AC bias current source configured to provide an AC bias current. The system also includes an amplifier coupled to the input stage and configured to generate a plurality of sequential SFQ pulses based on the input pulse in response to the AC bias current. The system further includes a low-pass filter configured to filter the plurality of sequential SFQ pulses to generate an amplified output pulse that is output to a transmission line.
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公开(公告)号：US10447278B1
公开(公告)日：2019-10-15
申请号：US16037587
申请日：2018-07-17
IPC分类号： H03K19/195 , H03K19/177 , G06N10/00 , G11C11/44
摘要： Superconducting logic arrays (SLAs) and field-programmable gate arrays (FPGAs) that are based on Josephson transmission lines (JTLs) accommodate reciprocal quantum logic (RQL) compliant binary input signals and provide RQL-compliant output signals that are evaluations of generalized logic functions. Each JTL-based superconducting FPGA (JTLBSFPGA) incorporates multiple JTL-based SLAs (JTLBSLAs) connected together. Each JTLBSLA includes an array of software-programmable and/or mask-programmed logic cells that output products of inputs and cell states, such that the JTLBSLAs output evaluations of sum-of-products functions. New JTLBSLA logic cells are described, including some that provide programmable cell states via magnetic Josephson junctions (MJJs). JTLBSFPGAs provide area efficiency and clock speed advantages over CMOS FPGAs. Unlike SLAs based on Josephson magnetic random access memory (JMRAM), JTLBSLAs do not require word line drivers, flux pumps, or sense amplifiers. Because JTLBSLAs and JTLBSFPGAs are RQL-compliant, they can also include RQL gates connected within or between them, without signal conversion circuitry.
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公开(公告)号：US10122351B1
公开(公告)日：2018-11-06
申请号：US15659005
申请日：2017-07-25
摘要： One example includes a superconducting bidirectional current driver. The current driver includes a first direction superconducting latch that is activated in response to a first activation signal and a second direction superconducting latch that is activated in response to a second activation signal. The second direction superconducting latch is activated to provide a first current path of an input current through the first direction superconducting latch and through a bidirectional current load in a first direction. The first direction superconducting latch is activated to provide a second current path of the input current through the second direction superconducting latch and through the bidirectional current load in a second direction opposite the first direction.
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公开(公告)号：US20230046568A1
公开(公告)日：2023-02-16
申请号：US17401526
申请日：2021-08-13
IPC分类号： H03M5/14 , H03K19/003
摘要： Edge-sensitive, state-based single flux quantum (SFQ) based circuitry and related methods convert return-to-zero (RZ) or non-return-to-zero (NRZ) encoded SFQ-pulse-based signals to bilevel NRZ phase signals that can subsequently be converted to bilevel voltage signals by an output amplifier (OA). The SFQ-based circuitry can be integrated with a current amplification stage of a driver that can be coupled to a stage of the OA. The SFQ-based circuitry can be made to be compatible with RQL-encoded input signals that can be either RZ or NRZ. The SFQ-based circuitry can thus be compatible with both wave-pipelined (WPL) and phase-mode (PML) RQL circuitry. Because the SFQ-based circuitry and related methods are edge-sensitive and state-based, they can function at system clock rates in excess of 1 GHz with reduced glitches and improved bit error rates as compared to other superconducting RZ-NRZ conversion circuitry and methods.
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公开(公告)号：US11342920B1
公开(公告)日：2022-05-24
申请号：US17142829
申请日：2021-01-06
IPC分类号： H03K19/21 , H03K19/195 , H01L39/22 , G06N10/00 , H03K3/38
摘要： One example includes a pulse selector system. The pulse selector system includes an input Josephson transmission line (JTL) configured to propagate an input reciprocal quantum logic (RQL) pulse received at an input based on a bias signal. The RQL pulse includes a fluxon and an antifluxon. The system also includes an escape Josephson junction coupled to an output of the input JTL. The escape Josephson junction can be configured to pass a selected one of the fluxon and the antifluxon of the RQL pulse and to trigger in response to the other of the fluxon and the antifluxon of the RQL pulse to block the other of the fluxon and the antifluxon of the RQL pulse. The system further includes an output JTL configured to propagate the selected one of the fluxon and the antifluxon as a unipolar pulse to an output based on the bias signal.
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