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公开(公告)号：US10554207B1
公开(公告)日：2020-02-04
申请号：US16051058
申请日：2018-07-31
申请人： Anna Y. Herr , Quentin P. Herr , Ryan Edward Clarke , Harold Clifton Hearne, III , Alexander Louis Braun , Randall M. Burnett , Timothy Chi-Chao Lee
发明人： Anna Y. Herr , Quentin P. Herr , Ryan Edward Clarke , Harold Clifton Hearne, III , Alexander Louis Braun , Randall M. Burnett , Timothy Chi-Chao Lee
IPC分类号： H03K19/195 , H03K3/38 , G11C11/44 , G06N10/00
摘要： Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.
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公开(公告)号：US11159168B2
公开(公告)日：2021-10-26
申请号：US17094452
申请日：2020-11-10
申请人： Anna Y. Herr , Quentin P. Herr , Ryan Edward Clarke , Harold Clifton Hearne, III , Alexander Louis Braun , Randall M. Burnett , Timothy Chi-Chao Lee
发明人： Anna Y. Herr , Quentin P. Herr , Ryan Edward Clarke , Harold Clifton Hearne, III , Alexander Louis Braun , Randall M. Burnett , Timothy Chi-Chao Lee
IPC分类号： H03K19/195 , G06N10/00 , G11C11/44 , H03K3/38
摘要： Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.
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公开(公告)号：US12045692B2
公开(公告)日：2024-07-23
申请号：US17736646
申请日：2022-05-04
申请人： Haitao O. Dai , Max E. Nielsen , Alexander Louis Braun , Daniel George Dosch , Kurt Pleim , Charles Ryan Wallace
发明人： Haitao O. Dai , Max E. Nielsen , Alexander Louis Braun , Daniel George Dosch , Kurt Pleim , Charles Ryan Wallace
IPC分类号： G06N10/40 , G01R33/035
CPC分类号： G06N10/40 , G01R33/0354
摘要： An output-amplifier-based reciprocal quantum logic (RQL) bias-level sensor is used to measure and/or calibrate bias parameters of AC and/or DC bias signals provided to RQL circuitry. The bias signals can include an output amplifier output bias current. The bias-level sensor includes a stack of DC SQUIDs that are supplied their inputs from outputs of respective Josephson transmission lines (JTLs) to which the SQUIDs are transformer-coupled. Staging relative strengths of the bias taps of the JTLs, or the critical currents of the Josephson junctions in the DC SQUIDs, allows an output voltage signal of the bias-level sensor to be indicative of whether a provided bias value is an improvement or optimization of the bias value when varied over a range. The outputs of two such bias-level sensors driven by I and Q clocks can be compared to adjust AC bias amplitudes of the clocks. Relative clock phase can be similarly adjusted.
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公开(公告)号：US11942937B2
公开(公告)日：2024-03-26
申请号：US17736517
申请日：2022-05-04
申请人： Charles Ryan Wallace , Max E. Nielsen , Alexander Louis Braun , Daniel George Dosch , Kurt Pleim , Haitao O. Dai
发明人： Charles Ryan Wallace , Max E. Nielsen , Alexander Louis Braun , Daniel George Dosch , Kurt Pleim , Haitao O. Dai
IPC分类号： H03K19/195 , H03K3/38 , H03K19/17736 , H03K19/20
CPC分类号： H03K19/195 , H03K3/38 , H03K19/1774 , H03K19/17744 , H03K19/20
摘要： Pulse-generator-based reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors include pulse generators having strengthened or weakened bias taps (transformer couplings to RQL AC clock resonators or DC bias lines) as compared to bias taps of Josephson transmission lines in the operational RQL circuitry, or Josephson junctions (JJs) with larger or smaller critical currents as compared to JJs in the operational RQL circuitry. Pulse generators with weakened bias taps or larger JJs can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. The bias-level sensors can be staged by relative strength to indicate whether a provided bias value is an improvement when varied over a range.
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公开(公告)号：US10171087B1
公开(公告)日：2019-01-01
申请号：US15810907
申请日：2017-11-13
IPC分类号： H03K19/195 , H03K3/38 , G11C11/44
摘要： Large fan-in logical gate circuits for use in reciprocal quantum logic (RQL) systems and related methods permit for improved efficiency and density of RQL logic. A majority 3-of-5 gate circuit, as described, can be extended to include more than five inputs, and can also be modified to create AND gates, OR gates, and OA gates. The gate circuits can accommodate inputs and provide outputs each in the form of single flux quantum (SFQ) pulses, either positive or negative, to indicate asserted and de-asserted logic states, respectively.
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公开(公告)号：US10756712B2
公开(公告)日：2020-08-25
申请号：US15810860
申请日：2017-11-13
IPC分类号： H03K3/38
摘要： A reciprocal quantum logic (RQL) phase-mode flip-flop includes a storage loop and a comparator, each of which includes Josephson junctions (JJs). A data input, provided as a positive or negative single flux quantum (SFQ) pulse, is stored in the storage loop to set the storage loop in a positive or negative state, respectively, effectively biasing an output JJ shared between the storage loop and a comparator. The data input is captured to the output upon the receipt of a logical clock SFQ reciprocal pulse pair to the comparator, when one of the pulses in the pair causes the output JJ to preferentially trigger over an escape junction in the comparator, owing to the output JJ having been biased by current in the storage loop.
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公开(公告)号：US10447279B1
公开(公告)日：2019-10-15
申请号：US16205959
申请日：2018-11-30
IPC分类号： H03K19/195 , H03K19/23
摘要： An inverting reciprocal quantum logic (RQL) phase-mode D flip-flop accepts a data input and a logical clock input. The flip-flop includes a stacked Josephson junction and a comparator. The triggering or untriggering of the stacked Josephson junction by positive or negative single flux quantum (SFQ) pulses can switch a direction of DC bias current through a component of the comparator, such as an output Josephson junction, which can then either pass or suppress logical clock SFQ pulses. When so passed, the data input is captured to the output upon clocking the flip-flop via the provision of the logical clock SFQ pulses, e.g., as reciprocal pulse pairs.
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公开(公告)号：US10158363B1
公开(公告)日：2018-12-18
申请号：US15811000
申请日：2017-11-13
IPC分类号： H03K19/195 , H03K19/20
摘要： A Josephson AND/OR gate circuit makes efficient use of Josephson junction (JJ) and inductor components to provide two-input, two-output AND/OR logical functions. The circuit includes four logical input storage loops that each contain one of two logical decision JJs that are configured such that they trigger to provide the OR and AND signals, respectively. Functional asymmetry is provided in the topologically symmetrical AND/OR gate circuit by a bias storage loop that includes both of the logical decision JJs and that is initialized to store a directional Φ0 of current at system start-up.
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公开(公告)号：US11804275B1
公开(公告)日：2023-10-31
申请号：US17736564
申请日：2022-05-04
申请人： Alexander Louis Braun , Max E. Nielsen , Daniel George Dosch , Kurt Pleim , Haitao O. Dai , Charles Ryan Wallace
发明人： Alexander Louis Braun , Max E. Nielsen , Daniel George Dosch , Kurt Pleim , Haitao O. Dai , Charles Ryan Wallace
CPC分类号： G11C19/32 , H03K3/037 , H03K3/38 , H03K19/195 , H03L7/0805 , H03L7/0816
摘要： Shift register elements of a phase-mode bit-addressable sensing register sample varied AC or DC bias values provided to operational RQL circuitry on the RQL IC via clock resonators or DC bias lines. The shift register can be constructed of phase-mode D flip-flops and JTLs as data and clock lines. A method of using the sensing register includes shifting in a data bit pattern while a bias parameter (e.g., AC amplitude, DC value, or phase) is set to a nominal value; stopping the logical clock that controls the shifting of values through the sensing register, varying the bias parameter value, inputting one assertion SFQ pulse or reciprocal pulse pair into the logical clock, restoring the bias parameter to the nominal value, restarting the logical clock to shift out an output data bit pattern, and observing the output data bit pattern to determine the effect of the bias parameter value change.
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公开(公告)号：US11569821B2
公开(公告)日：2023-01-31
申请号：US17354603
申请日：2021-06-22
IPC分类号： H03K19/21 , H03K3/38 , H03K19/195
摘要： One example describes a superconducting XOR-gate system. The system includes a pulse generator configured to generate a decision pulse. The system also includes an input superconducting XOR-2 gate that receives a first superconducting logic input signal and a second superconducting logic input signal and is configured to perform a logic XOR function based on the decision pulse on a given phase of a clock signal to provide an intermediate superconducting logic output signal. The system also includes an output superconducting XOR-2 gate that receives the intermediate superconducting logic output signal and a third superconducting logic input signal and is configured to perform a logic XOR function based on the decision pulse on the given phase of the clock signal to provide a superconducting logic output signal.
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