公开(公告)号：US20120161202A1

公开(公告)日：2012-06-28

申请号：US12978248

申请日：2010-12-23

申请人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Titash Rakshit ,  Sivakumar P. Mudanai

发明人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Titash Rakshit ,  Sivakumar P. Mudanai

IPC分类号： H01L29/772 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L29/775 ,  H01L29/0669 ,  H01L29/205 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7857

摘要： A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.

摘要翻译： 通过在JAM半导体主体的突出特征之下的反向偏压带将无连接累积模式（JAM）半导体器件从半导体衬底隔离。 制造JAM器件的过程包括植入和外延。

公开(公告)号：US08507948B2

公开(公告)日：2013-08-13

申请号：US12978248

申请日：2010-12-23

申请人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Titash Rakshit ,  Sivakumar P. Mudanai

发明人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Titash Rakshit ,  Sivakumar P. Mudanai

IPC分类号： H01L29/66

CPC分类号： H01L29/775 ,  H01L29/0669 ,  H01L29/205 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7857

摘要： A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconductive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.

摘要翻译： 无连接累积模式（JAM）半导体器件通过JAM半导体的突出特征之下的反向偏压带从半导体衬底隔离。 制造JAM器件的过程包括植入和外延。

公开(公告)号：US08753942B2

公开(公告)日：2014-06-17

申请号：US12958179

申请日：2010-12-01

申请人： Kelin J. Kuhn ,  Seiyon Kim ,  Rafael Rios ,  Stephen M. Cea ,  Martin D. Giles ,  Annalisa Cappellani ,  Titash Rakshit ,  Peter Chang ,  Willy Rachmady

发明人： Kelin J. Kuhn ,  Seiyon Kim ,  Rafael Rios ,  Stephen M. Cea ,  Martin D. Giles ,  Annalisa Cappellani ,  Titash Rakshit ,  Peter Chang ,  Willy Rachmady

IPC分类号： H01L29/775 ,  H01L29/66 ,  H01L21/336 ,  H01L21/762 ,  H01L29/772 ,  B82Y40/00

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间​​的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

公开(公告)号：US20120138886A1

公开(公告)日：2012-06-07

申请号：US12958179

申请日：2010-12-01

申请人： Kelin J. Kuhn ,  Seiyon Kim ,  Rafael Rios ,  Stephen M. Cea ,  Martin D. Giles ,  Annalisa Cappellani ,  Titash Rakshit ,  Peter Chang ,  Willy Rachmady

发明人： Kelin J. Kuhn ,  Seiyon Kim ,  Rafael Rios ,  Stephen M. Cea ,  Martin D. Giles ,  Annalisa Cappellani ,  Titash Rakshit ,  Peter Chang ,  Willy Rachmady

IPC分类号： H01L29/775 ,  H01L29/66 ,  H01L21/336 ,  H01L21/762 ,  B82Y40/00 ,  H01L29/772

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间​​的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

公开(公告)号：US09129829B2

公开(公告)日：2015-09-08

申请号：US14274592

申请日：2014-05-09

申请人： Kelin J. Kuhn ,  Seiyon Kim ,  Rafael Rios ,  Stephen M. Cea ,  Martin D. Giles ,  Annalisa Cappellani ,  Titash Rakshit ,  Peter Chang ,  Willy Rachmady

发明人： Kelin J. Kuhn ,  Seiyon Kim ,  Rafael Rios ,  Stephen M. Cea ,  Martin D. Giles ,  Annalisa Cappellani ,  Titash Rakshit ,  Peter Chang ,  Willy Rachmady

IPC分类号： H01L29/165 ,  H01L29/06 ,  B82Y10/00 ,  H01L21/762 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间​​的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

公开(公告)号：US20130334572A1

公开(公告)日：2013-12-19

申请号：US13964696

申请日：2013-08-12

申请人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Titash Rakshit ,  Sivakumar Mudanai

发明人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Titash Rakshit ,  Sivakumar Mudanai

IPC分类号： H01L29/205 ,  H01L29/78

CPC分类号： H01L29/775 ,  H01L29/0669 ,  H01L29/205 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7857

摘要： A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.

摘要翻译： 通过在JAM半导体主体的突出特征之下的反向偏压带将无连接累积模式（JAM）半导体器件从半导体衬底隔离。 制造JAM器件的过程包括植入和外延。

公开(公告)号：US10424580B2

公开(公告)日：2019-09-24

申请号：US13996505

申请日：2011-12-23

申请人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Gopinath Bhimarasetti ,  Tahir Ghani ,  Seiyon Kim

发明人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Gopinath Bhimarasetti ,  Tahir Ghani ,  Seiyon Kim

IPC分类号： H01L29/775 ,  H01L21/02 ,  H01L27/088 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/16 ,  B82Y99/00

摘要： Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.

公开(公告)号：US09583491B2

公开(公告)日：2017-02-28

申请号：US14948083

申请日：2015-11-20

申请人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

发明人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L21/84 ,  H01L29/423 ,  H01L29/10

CPC分类号： H01L21/823821 ,  B82Y10/00 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/12 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.

摘要翻译： 描述了免费的金属氧化物半导体纳米线结构。 例如，半导体结构包括第一半导体器件。 第一半导体器件包括设置在衬底之上的第一纳米线。 第一纳米线具有在衬底上方的第一距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一栅极电极堆叠完全包围第一纳米线的离散通道区域。 半导体结构还包括第二半导体器件。 第二半导体器件包括设置在衬底上方的第二纳米线。 第二纳米线在衬底上方具有第二距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一距离与第二距离不同。 第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。

公开(公告)号：US20130313513A1

公开(公告)日：2013-11-28

申请号：US13996505

申请日：2011-12-23

申请人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Gopinath Bhimarasetti ,  Tahir Ghani ,  Seiyon Kim

发明人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Gopinath Bhimarasetti ,  Tahir Ghani ,  Seiyon Kim

IPC分类号： H01L29/775 ,  H01L21/02 ,  H01L27/088

摘要： Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.

摘要翻译： 描述了具有调制纳米线计数的半导体器件和形成这种器件的方法。 例如，半导体结构包括具有多个纳米线的第一半导体器件，该多个纳米线设置在衬底上并且堆叠在具有第一最上层纳米线的第一垂直平面中。 第二半导体器件具有设置在衬底上方的一个或多个纳米线并且堆叠在具有第二最上层纳米线的第二垂直平面中。 第二半导体器件包括比第一半导体器件少的一个或多个纳米线。 第一和第二最上层的纳米线设置在与第一和第二垂直平面正交的同一平面中。

公开(公告)号：US09425212B2

公开(公告)日：2016-08-23

申请号：US13538822

申请日：2012-06-29

申请人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Harry Gomez

发明人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Harry Gomez

IPC分类号： H01L27/088 ,  H01L21/76 ,  H01L27/12 ,  H01L21/762

CPC分类号： H01L21/76237 ,  H01L21/76232 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/7851

摘要： Isolated and bulk semiconductor devices formed on a same bulk substrate and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed on a bulk substrate. The first semiconductor body has an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed on an isolation pedestal. The isolation pedestal is disposed on the bulk substrate. The second semiconductor body has an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar.

摘要翻译： 描述了形成在相同体积基板上的隔离和体半导体器件以及形成这种器件的方法。 例如，半导体结构包括具有设置在体基板上的第一半导体本体的第一半导体器件。 第一半导体本体具有带有第一水平面的最上表面。 半导体结构还包括具有设置在隔离基座上的第二半导体本体的第二半导体器件。 隔离基座设置在主体基板上。 第二半导体本体具有带有第二水平面的最上表面。 第一和第二水平面是共面的。