公开(公告)号：US08924617B2

公开(公告)日：2014-12-30

申请号：US12429833

申请日：2009-04-24

Applicant: Milivoje Aleksic ,  Raymond M. Li ,  Danny H. M. Cheng ,  Carl K. Mizuyabu ,  Anthony Asaro

Inventor： Milivoje Aleksic ,  Raymond M. Li ,  Danny H. M. Cheng ,  Carl K. Mizuyabu ,  Anthony Asaro

IPC: G06F13/14 ,  G09G5/39 ,  G06T1/60 ,  G09G5/393

CPC classification number: G06T1/60 ,  G06F13/1663 ,  G06F13/1684 ,  G06F13/28 ,  G06T1/20 ,  G09G5/39 ,  G09G5/393 ,  G09G2360/125

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.

Abstract translation: 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。

公开(公告)号：US20110264934A1

公开(公告)日：2011-10-27

申请号：US12767460

申请日：2010-04-26

Applicant: Alexander Branover ,  Maurice B. Steinman ,  Anthony Asaro ,  James B. Fry

Inventor： Alexander Branover ,  Maurice B. Steinman ,  Anthony Asaro ,  James B. Fry

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  G06F1/3287 ,  G11C5/148 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

Abstract: A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if at least a first amount of time has elapsed since any one of the processor cores has asserted a memory access request and determining if at least a second amount of time has elapsed since the I/O unit has conveyed a memory access request. A first signal may be asserted if the first and second amounts of time have elapsed. A memory subsystem may be transitioned from operating in a full power state to a first low power state responsive to assertion of the first signal.

Abstract translation: 公开了一种用于电力管理的方法。 该方法可以包括监视由一个或多个处理器核访问存储器子系统的存储器的请求; 以及监视对由输入/输出（I / O）单元传送的存储器的访问请求。 该方法还可以包括确定是否已经过去了至少第一时间量，因为处理器核心已经确定了存储器访问请求并且确定自I / O单元是否已经传送了至少第二时间量 内存访问请求。 如果第一和第二时间量已经过去，则可以断言第一信号。 存储器子系统可以响应于第一信号的断言而从全功率状态工作转变到第一低功率状态。

公开(公告)号：US20090077274A1

公开(公告)日：2009-03-19

申请号：US11857984

申请日：2007-09-19

Applicant: Gordon F. Caruk ,  Anthony Asaro

Inventor： Gordon F. Caruk ,  Anthony Asaro

IPC: G06F3/00

CPC classification number: G06F13/4278 ,  Y02D10/14 ,  Y02D10/151

Abstract: A circuit includes a high priority circuit and a non-high priority circuit. The high priority circuit is operative to communicate high priority information to a single path of a differential serial communication link. The non-high priority circuit communicates non-high priority information to the single path. The high priority information is communicated prior to the non-high priority information. In one example, the circuit includes a flow control distributor operatively coupled to the high priority circuit and the non-high priority circuit. The flow control distributor distributes a total number of flow control credits into high priority credits and non-high priority credits. The flow control distributor controls communication of the high priority information based on the high priority credits. The flow control distributor controls communication of the non-high priority information based on the non-high priority credits.

Abstract translation: 电路包括高优先级电路和非高优先级电路。 高优先级电路用于将高优先级信息传送到差分串行通信链路的单个路径。 非高优先级电路将非高优先级信息传送到单路径。 在非高优先级信息之前传送高优先级信息。 在一个示例中，电路包括可操作地耦合到高优先级电路和非高优先级电路的流量控制分配器。 流量控制分配器将总数量的流量控制信用分配到高优先级信用和非高优先级信用。 流量控制分配器基于高优先级信用来控制高优先级信息的通信。 流量控制分配器基于非高优先级信用来控制非高优先级信息的通信。

公开(公告)号：US09152571B2

公开(公告)日：2015-10-06

申请号：US13563253

申请日：2012-07-31

Applicant: Andrew G. Kegel ,  Mark D. Hummel ,  Anthony Asaro

Inventor： Andrew G. Kegel ,  Mark D. Hummel ,  Anthony Asaro

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/1081 ,  G06F2212/683

Abstract: An input/output memory management unit (IOMMU) having an “invalidate all” command available to clear the contents of cache memory is presented. The cache memory provides fast access to address translation data that has been previously obtained by a process. A typical cache memory includes device tables, page tables and interrupt remapping entries. Cache memory data can become stale or be compromised from security breaches or malfunctioning devices. In these circumstances, a rapid approach to clearing cache memory content is provided.

Abstract translation: 提供具有可用于清除高速缓冲存储器的内容的“无效全部”命令的输入/输出存储器管理单元（IOMMU）。 缓存存储器可以快速访问以前由进程获取的地址转换数据。 典型的高速缓存包括设备表，页表和中断重映射条目。 高速缓存存储器数据可能会变得过时或者从安全漏洞或故障设备中泄露出来。 在这些情况下，提供了快速清除缓存存储器内容的方法。

公开(公告)号：US08656198B2

公开(公告)日：2014-02-18

申请号：US12767460

申请日：2010-04-26

Applicant: Alexander Branover ,  Maurice B. Steinman ,  Anthony Asaro ,  James B. Fry

Inventor： Alexander Branover ,  Maurice B. Steinman ,  Anthony Asaro ,  James B. Fry

IPC: G06F1/00

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  G06F1/3287 ,  G11C5/148 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

Abstract: A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if at least a first amount of time has elapsed since any one of the processor cores has asserted a memory access request and determining if at least a second amount of time has elapsed since the I/O unit has conveyed a memory access request. A first signal may be asserted if the first and second amounts of time have elapsed. A memory subsystem may be transitioned from operating in a full power state to a first low power state responsive to assertion of the first signal.

Abstract translation: 公开了一种用于电力管理的方法。 该方法可以包括监视由一个或多个处理器核访问存储器子系统的存储器的请求; 以及监视对由输入/输出（I / O）单元传送的存储器的访问请求。 该方法还可以包括确定是否已经过去了至少第一时间量，因为处理器核心已经确定了存储器访问请求并且确定自I / O单元是否已经传送了至少第二时间量 内存访问请求。 如果第一和第二时间量已经过去，则可以断言第一信号。 存储器子系统可以响应于第一信号的断言而从全功率状态工作转变到第一低功率状态。

公开(公告)号：US20130263141A1

公开(公告)日：2013-10-03

申请号：US13588310

申请日：2012-08-17

Applicant: Anthony Asaro ,  Kevin Normoyle ,  Mark Hummel

Inventor： Anthony Asaro ,  Kevin Normoyle ,  Mark Hummel

IPC: G06F9/46

CPC classification number: G06F9/46 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/52

Abstract: Provided is a method of permitting the reordering of a visibility order of operations in a computer arrangement configured for permitting a first processor and a second processor threads to access a shared memory. The method includes receiving in a program order, a first and a second operation in a first thread and permitting the reordering of the visibility order for the operations in the shared memory based on the class of each operation. The visibility order determines the visibility in the shared memory, by a second thread, of stored results from the execution of the first and second operations.

Abstract translation: 提供了一种允许重新排序配置为允许第一处理器和第二处理器线程访问共享存储器的计算机配置中的操作的可见性顺序的方法。 该方法包括以程序顺序接收第一线程中的第一和第二操作，并且基于每个操作的类别允许对共享存储器中的操作的可见性顺序的重新排序。 可见性顺序确定共享存储器（第二个线程）中可执行第一和第二操作的存储结果的可见性。

公开(公告)号：US08495300B2

公开(公告)日：2013-07-23

申请号：US12716391

申请日：2010-03-03

Applicant: Philip Ng ,  Jimshed B. Mirza ,  Anthony Asaro

Inventor： Philip Ng ,  Jimshed B. Mirza ,  Anthony Asaro

IPC: G06F13/00

CPC classification number: G06F12/0862 ,  G06F12/0868 ,  G06F2212/1028 ,  G06F2212/6024 ,  Y02D10/13

Abstract: A method and apparatus for repopulating a cache are disclosed. At least a portion of the contents of the cache are stored in a location separate from the cache. Power is removed from the cache and is restored some time later. After power has been restored to the cache, it is repopulated with the portion of the contents of the cache that were stored separately from the cache.

Abstract translation: 公开了一种用于重新填充缓存的方法和装置。 缓存的内容的至少一部分被存储在与高速缓存分开的位置。 电源从缓存中删除，并在稍后恢复。 在电源恢复到缓存之后，它将重新填充与高速缓存单独存储的高速缓存的内容部分。

公开(公告)号：US20130145055A1

公开(公告)日：2013-06-06

申请号：US13309753

申请日：2011-12-02

Applicant: Andrew Kegel ,  Mark Hummel ,  Anthony Asaro ,  Phillip NG

Inventor： Andrew Kegel ,  Mark Hummel ,  Anthony Asaro ,  Phillip NG

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F12/0223 ,  G06F12/1081 ,  G06F2213/0058

Abstract: The present system enables an input/output (I/O) device to request memory for performing a direct memory access (DMA) of system memory. Further, the system uses an input/output memory management unit (IOMMU) to determine whether or not the system memory is available. The IOMMU notifies an operating system associated with the system memory if the system memory is not available, such that the operating system allocates non-system memory for use by the I/O device to perform the DMA.

Abstract translation: 本系统使得输入/输出（I / O）设备能够请求存储器来执行系统存储器的直接存储器访问（DMA）。 此外，系统使用输入/输出存储器管理单元（IOMMU）来确定系统存储器是否可用。 如果系统内存不可用，IOMMU将通知与系统内存相关联的操作系统，以便操作系统分配非系统内存供I / O设备使用以执行DMA。

公开(公告)号：US20110219190A1

公开(公告)日：2011-09-08

申请号：US12716391

申请日：2010-03-03

Applicant: Philip Ng ,  Jimshed B. Mirza ,  Anthony Asaro

Inventor： Philip Ng ,  Jimshed B. Mirza ,  Anthony Asaro

IPC: G06F12/08 ,  G06F1/24

CPC classification number: G06F12/0862 ,  G06F12/0868 ,  G06F2212/1028 ,  G06F2212/6024 ,  Y02D10/13

Abstract: A method and apparatus for repopulating a cache are disclosed. At least a portion of the contents of the cache are stored in a location separate from the cache. Power is removed from the cache and is restored some time later. After power has been restored to the cache, it is repopulated with the portion of the contents of the cache that were stored separately from the cache.

Abstract translation: 公开了一种用于重新填充缓存的方法和装置。 缓存的内容的至少一部分被存储在与高速缓存分开的位置。 电源从缓存中删除，并在稍后恢复。 在电源恢复到缓存之后，它将重新填充与高速缓存单独存储的高速缓存的内容部分。

公开(公告)号：US07805560B2

公开(公告)日：2010-09-28

申请号：US11162165

申请日：2005-08-31

Applicant: Anthony Asaro ,  Joe Scanlon ,  Bo Liu

Inventor： Anthony Asaro ,  Joe Scanlon ,  Bo Liu

IPC: G06F13/36 ,  G06F13/20 ,  G06F15/16 ,  G06F13/00 ,  G06F9/34 ,  H04L12/56

CPC classification number: G06F13/404 ,  G06F2213/0026

Abstract: Methods and apparatus for translating messages in a computing system are disclosed. In particular, a disclosed method for converting messages in a computer system includes receiving a command message from a processing unit where the message is defined according to a transport protocol that utilizes command messages using an address to communicate commands to devices in the computer system. The command message is translated to an interface standard by mapping the address into an address field of a packet constructed according to the interface standard. Corresponding apparatus that perform the methods are also disclosed.

Abstract translation: 公开了用于在计算系统中翻译消息的方法和装置。 具体地，所公开的用于在计算机系统中转换消息的方法包括从处理单元接收命令消息，其中根据传输协议来定义消息，该传输协议利用使用地址的命令消息来向计算机系统中的设备传送命令。 通过将地址映射到根据接口标准构造的分组的地址字段中，将命令消息转换为接口标准。 还公开了执行该方法的相应装置。