利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

292 条记录 (耗时 0.034 秒)

    Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby
    1.
    发明授权
    Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby 有权
    用于分别优化同一半导体芯片内的PMOS和NMOS晶体管的薄栅极电介质及其制造的器件的方法

    公开(公告)号：US06821833B1

    公开(公告)日：2004-11-23

    申请号：US10605110

    申请日：2003-09-09

    申请人： Anthony I-Chih Chou ,  Toshiharu Furukawa ,  Patrick R. Varekamp ,  Jeffrey W. Sleight ,  Akihisa Sekiguchi

    发明人： Anthony I-Chih Chou ,  Toshiharu Furukawa ,  Patrick R. Varekamp ,  Jeffrey W. Sleight ,  Akihisa Sekiguchi

    IPC分类号： H01L218238

    CPC分类号： H01L21/28202 ,  H01L21/823842 ,  H01L21/823857

    摘要： A method of forming CMOS semiconductor materials with PFET and NFET areas formed on a semiconductor substrate, covered respectively with a PFET and NFET gate dielectric layers composed of silicon oxide and different degrees of nitridation thereof. Provide a silicon substrate with a PFET area and an NFET area and form PFET and NFET gate oxide layers thereover. Provide nitridation of the PFET gate oxide layer above the PFET area to form the PFET gate dielectric layer above the PFET area with a first concentration level of nitrogen atoms in the PFET gate dielectric layer above the PFET area. Provide nitridation of the NFET gate oxide layer to form the NFET gate dielectric layer above the NFET area with a different concentration level of nitrogen atoms from the first concentration level. The NFET gate dielectric layer and the PFET gate dielectric layer can have the same thickness.

    摘要翻译： 一种形成在半导体衬底上的PFET和NFET区域的CMOS半导体材料的方法，分别覆盖由氧化硅和不同程度的氮化构成的PFET和NFET栅极电介质层。 为硅衬底提供PFET区域和NFET区域，并在其上形成PFET和NFET栅极氧化物层。 在PFET区域上方提供PFET栅极氧化物层的氮化，以在PFET区域上方形成PFET栅极电介质层上的PFET栅极电介质层，在PFET区域上方的PFET栅极电介质层中具有氮原子的第一浓度水平。 提供NFET栅极氧化物层的氮化，以在NFET区域上方形成具有与第一浓度水平不同的氮原子浓度水平的NFET栅极电介质层。 NFET栅极电介质层和PFET栅极电介质层可以具有相同的厚度。

    Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)
    3.
    发明授权
    Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) 有权
    绝缘体上半导体（SOI）结构包括梯度氮化掩埋氧化物（BOX）

    公开(公告)号：US07396776B2

    公开(公告)日：2008-07-08

    申请号：US11483901

    申请日：2006-07-10

    申请人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    发明人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    IPC分类号： H01L21/00

    CPC分类号： H01L29/78603 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.

    摘要翻译： 绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。 掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。 掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。 包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间。

    SEMICONDUCTOR-ON-INSULATOR(SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX)
    4.
    发明申请
    SEMICONDUCTOR-ON-INSULATOR(SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX) 有权
    半导体绝缘体（SOI）结构，包括梯度氮化氧化物（BOX）

    公开(公告)号：US20080224256A1

    公开(公告)日：2008-09-18

    申请号：US12123706

    申请日：2008-05-20

    申请人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    发明人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    IPC分类号： H01L23/58 ,  H01L21/762

    CPC分类号： H01L29/78603 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer

    摘要翻译： 绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。 掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。 掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。 包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间

    SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX)
    5.
    发明申请
    SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX) 有权
    半导体绝缘体（SOI）结构，包括梯度氮化氧化物（BOX）

    公开(公告)号：US20120049317A1

    公开(公告)日：2012-03-01

    申请号：US13290634

    申请日：2011-11-07

    申请人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    发明人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    IPC分类号： H01L29/12

    CPC分类号： H01L29/78603 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.

    摘要翻译： 绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。 掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。 掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。 包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间。

    Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)
    6.
    发明授权
    Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) 有权
    绝缘体上半导体（SOI）结构包括梯度氮化掩埋氧化物（BOX）

    公开(公告)号：US08288826B2

    公开(公告)日：2012-10-16

    申请号：US13290634

    申请日：2011-11-07

    申请人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    发明人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    IPC分类号： H01L29/76 ,  H01L21/00

    CPC分类号： H01L29/78603 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.

    摘要翻译： 绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。 掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。 掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。 包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间。

    Semiconductor-on-insulator(SOI) structures including gradient nitrided buried oxide (BOX)
    7.
    发明授权
    Semiconductor-on-insulator(SOI) structures including gradient nitrided buried oxide (BOX) 有权
    绝缘体上半导体（SOI）结构包括梯度氮化掩埋氧化物（BOX）

    公开(公告)号：US08053373B2

    公开(公告)日：2011-11-08

    申请号：US12123706

    申请日：2008-05-20

    申请人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    发明人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    IPC分类号： H01L21/31 ,  H01L29/76

    CPC分类号： H01L29/78603 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.

    摘要翻译： 绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。 掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。 掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。 包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间。