3D NAND STAIRCASE CD CONTROL BY USING INTERFEROMETRIC ENDPOINT DETECTION
    2.
    发明申请
    3D NAND STAIRCASE CD CONTROL BY USING INTERFEROMETRIC ENDPOINT DETECTION 有权
    通过使用干涉性端点检测的3D NAND STAIRCASE CD控制

    公开(公告)号:US20160099187A1

    公开(公告)日:2016-04-07

    申请号:US14968149

    申请日:2015-12-14

    Inventor: Lei LIAN

    Abstract: Embodiments of the present disclosure provide methods for forming stair-like structures in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method includes performing a trimming process on a substrate to trim a patterned photoresist layer disposed on a film stack from a first width to a second width in a processing chamber, performing an etching process to etch a portion of the film stack exposed by the trimmed patterned photoresist layer, directing an optical signal to a surface of the trimmed patterned photoresist layer continuously during the trimming and the etching process, collecting a return reflected optical signal reflected from the trimmed patterned photoresist layer, determining a change of reflected intensify of the return reflected optical signal as collected; and calculating a photoresist thickness loss based on the change of the reflected intensity.

    Abstract translation: 本公开的实施例提供了在制造半导体芯片的三维(3D)堆叠中形成阶梯状结构的方法。 在一个示例中,一种方法包括在衬底上执行修剪处理以在处理室中从第一宽度到第二宽度修整设置在膜堆叠上的图案化光致抗蚀剂层,执行蚀刻工艺以蚀刻膜堆叠的一部分 通过修整的图案化光致抗蚀剂层曝光,在修剪和蚀刻过程期间连续地将光学信号引导到修剪的图案化光致抗蚀剂层的表面,收集从修整的图案化光致抗蚀剂层反射的返回反射光信号,确定反射增强的变化 的反射光信号收集; 并基于反射强度的变化计算光致抗蚀剂厚度损失。

    ETALON THERMOMETRY FOR PLASMA ENVIRONMENTS

    公开(公告)号:US20230102821A1

    公开(公告)日:2023-03-30

    申请号:US17487993

    申请日:2021-09-28

    Abstract: A method and apparatus for determining the temperature of a substrate within a processing chamber are described herein. The methods and apparatus described herein utilize an etalon assembly and a heterodyning effect to determine a first temperature of a substrate. The first temperature of the substrate is determined without physically contacting the substrate. A separate temperature sensor also measures a second temperature of the substrate and/or the substrate support at a similar location. The first temperature and the second temperature are utilized to calibrate one of the temperature sensors disposed within the substrate support, a model of the processes performed within the processing chamber, or to adjust a process parameter of the process performed within the processing chamber.

    OPTICAL CABLE FOR INTERFEROMETRIC ENDPOINT DETECTION

    公开(公告)号:US20220148862A1

    公开(公告)日:2022-05-12

    申请号:US17096829

    申请日:2020-11-12

    Inventor: Lei LIAN Pengyu HAN

    Abstract: Disclosed herein is an endpoint detection having an optical bundle configured to emit light through a ceiling of a processing chamber. The optical bundle has a plurality of fibers configured to transmit the light from a light source towards a substrate and is configured to receive light reflected from the substrate. The plurality of fibers include a first emitting fiber and a first receiving fiber. The first receiving fiber is radially disposed at a pairing angle from the first emitting fiber, and is configured to receive light emitted from the first emitting fiber. The plurality of fibers further include a second emitting fiber and a second receiving fiber. The second receiving fiber is radially disposed at the pairing angle from the second emitting fiber. The second receiving fiber is configured to receive light originating from the second emitting fiber. The pairing angle is between about 175 degrees and 185 degrees.

    TILTED INTERFEROMETRIC ENDPOINT (IEP) WINDOW FOR SENSITIVITY IMPROVEMENT

    公开(公告)号:US20200013588A1

    公开(公告)日:2020-01-09

    申请号:US16026486

    申请日:2018-07-03

    Inventor: Lei LIAN Pengyu HAN

    Abstract: A tilted window for use in an endpoint detection system of a processing chamber, and a processing chamber having the same are described herein. In one example, the tilted window includes a mounting frame, and a panel mounted in the mounting frame. The mounting frame has a body having a top surface, a bottom surface, and an inner edge connecting the top surface to the bottom surface of the body of the mounting frame. The mounting frame further has a panel disposed in the mounting frame. The panel has a body having a top surface and a bottom surface. The top surface of the body of the panel is oriented at acute angle relative to the top surface of the body of the mounting frame.

    ETALON THERMOMETRY FOR PLASMA ENVIRONMENTS

    公开(公告)号:US20240385048A1

    公开(公告)日:2024-11-21

    申请号:US18789641

    申请日:2024-07-30

    Abstract: A method and apparatus for determining the temperature of a substrate within a processing chamber are described herein. The methods and apparatus described herein utilize an etalon assembly and a heterodyning effect to determine a first temperature of a substrate. The first temperature of the substrate is determined without physically contacting the substrate. A separate temperature sensor also measures a second temperature of the substrate and/or the substrate support at a similar location. The first temperature and the second temperature are utilized to calibrate one of the temperature sensors disposed within the substrate support, a model of the processes performed within the processing chamber, or to adjust a process parameter of the process performed within the processing chamber.

    3D NAND STAIRCASE CD CONTROL BY USING INTERFEROMETRIC ENDPOINT DETECTION
    8.
    发明申请
    3D NAND STAIRCASE CD CONTROL BY USING INTERFEROMETRIC ENDPOINT DETECTION 有权
    通过使用干涉性端点检测的3D NAND STAIRCASE CD控制

    公开(公告)号:US20150011027A1

    公开(公告)日:2015-01-08

    申请号:US14326442

    申请日:2014-07-08

    Inventor: Lei LIAN

    Abstract: Embodiments of the present disclosure provide methods for forming stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips using precise photoresist trimming process endpoint control. In one example, a method of determining a photoresist trimming endpoint for forming stair-like structures on a substrate includes performing a trimming process on a substrate to trim a patterned photoresist layer disposed on a film stack from a first width to a second width in a processing chamber, wherein the patterned photoresist layer exposes a portion of the film stack uncovered by the patterned photoresist layer during the trimming process, directing an optical signal to a surface of the patterned photoresist layer while trimming the patterned photoresist layer, collecting a return reflected optical signal reflected from the photoresist layer, and determining a trimming endpoint by analyzing the return optical signal reflected from the photoresist layer.

    Abstract translation: 本公开的实施例提供了使用精确的光刻胶修剪过程端点控制来制造半导体芯片的三维(3D)堆叠来形成具有精确轮廓控制的阶梯状结构的方法。 在一个示例中,确定用于在衬底上形成阶梯状结构的光致抗蚀剂修剪端点的方法包括在衬底上执行修整处理以在第一宽度至第二宽度上修整设置在膜堆叠上的图案化光致抗蚀剂层 处理室,其中图案化的光致抗蚀剂层在修剪过程期间暴露由图案化的光致抗蚀剂层未覆盖的膜堆叠的一部分,将光信号引导到图案化的光致抗蚀剂层的表面,同时修整图案化的光致抗蚀剂层,收集返回反射的光 从光致抗蚀剂层反射的信号,以及通过分析从光致抗蚀剂层反射的返回光信号来确定修剪终点。

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