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    CARBON ADDITION FOR LOW RESISTIVITY IN SITU DOPED SILICON EPITAXY
    4.
    发明申请
    CARBON ADDITION FOR LOW RESISTIVITY IN SITU DOPED SILICON EPITAXY 审中-公开
    用于低电阻率的碳添加剂在原位硅胶外延中

    公开(公告)号：US20150221730A1

    公开(公告)日：2015-08-06

    申请号：US14688512

    申请日：2015-04-16

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Zhiyuan YE ,  Xuebin LI ,  Saurabh CHOPRA ,  Yihwan KIM

    IPC: H01L29/36 ,  H01L29/167

    CPC classification number: H01L29/36 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02664 ,  H01L21/823814 ,  H01L29/167 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

    Abstract: Embodiments of the present invention generally relate to methods of forming epitaxial layers and devices having epitaxial layers. The methods generally include forming a first epitaxial layer including phosphorus and carbon on a substrate, and then forming a second epitaxial layer including phosphorus and carbon on the first epitaxial layer. The second epitaxial layer has a lower phosphorus concentration than the first epitaxial layer, which allows for selective etching of the second epitaxial layer and undesired amorphous silicon or polysilicon deposited during the depositions. The substrate is then exposed to an etchant to remove the second epitaxial layer and undesired amorphous silicon or polysilicon. The carbon present in the first and second epitaxial layers reduces phosphorus diffusion, which allows for higher phosphorus doping concentrations. The increased phosphorus concentrations reduce the resistivity of the final device. The devices include epitaxial layers having a resistivity of less than about 0.381 milliohm-centimeters.

    Abstract translation: 本发明的实施例一般涉及形成外延层的方法和具有外延层的器件。 所述方法通常包括在衬底上形成包括磷和碳的第一外延层，然后在第一外延层上形成包括磷和碳的第二外延层。 第二外延层具有比第一外延层更低的磷浓度，其允许在沉积期间沉积的第二外延层和不期望的非晶硅或多晶硅的选择性蚀刻。 然后将衬底暴露于蚀刻剂以除去第二外延层和不期望的非晶硅或多晶硅。 存在于第一和第二外延层中的碳减少磷扩散，这允许更高的磷掺杂浓度。 增加的磷浓度降低了最终装置的电阻率。 这些器件包括具有小于约0.381毫欧姆厘米的电阻率的外延层。

    MOVABLE CENTRAL REFLECTORS OF SEMICONDUCTOR PROCESSING EQUIPMENT, AND RELATED SYSTEMS AND METHODS
    5.
    发明公开
    MOVABLE CENTRAL REFLECTORS OF SEMICONDUCTOR PROCESSING EQUIPMENT, AND RELATED SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20240360587A1

    公开(公告)日：2024-10-31

    申请号：US18223345

    申请日：2023-07-18

    Applicant: Applied Materials, Inc.

    Inventor： Ala MORADIAN ,  Vishwas Kumar PANDEY ,  Lori D. WASHINGTON ,  Saurabh CHOPRA

    IPC: C30B25/10 ,  C23C16/46

    CPC classification number: C30B25/10 ,  C23C16/46

    Abstract: The present disclosure relates to a radiation reflector assembly for use with a semiconductor processing chamber and a substrate processing system having the radiation reflector assembly. The radiation reflector assembly includes a shell body that includes an interior cylindrical wall; and a reflector disk that includes a center hole, a bottom reflective surface, and a top surface. The reflector disk is disposed within and spaced from the interior cylindrical wall in a manner that permits fluid to flow therebetween. The radiation reflector assembly includes an actuator coupled to the reflector disk, and the actuator is operable to axially displace the reflector disk relative to the shell body. The radiation reflector assembly includes an elongated tube extending through the center hole of the reflector disk. A method of processing a substrate with the radiation reflector assembly is also described.

    SEMICONDUCTOR DEVICE, METHOD OF MAKING A SEMICONDUCTOR DEVICE, AND PROCESSING SYSTEM
    7.
    发明申请
    SEMICONDUCTOR DEVICE, METHOD OF MAKING A SEMICONDUCTOR DEVICE, AND PROCESSING SYSTEM 审中-公开

    公开(公告)号：US20200258997A1

    公开(公告)日：2020-08-13

    申请号：US16773848

    申请日：2020-01-27

    Applicant: Applied Materials, Inc.

    Inventor： Gaurav THAREJA ,  Xuebin LI ,  Abhishek DUBE ,  Yi-Chiau HUANG ,  Andy LO ,  Patricia M. LIU ,  Sanjay NATARAJAN ,  Saurabh CHOPRA

    IPC: H01L29/45 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/40

    Abstract: The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device. Embodiments of the present disclosure enable formation of a source/drain contact with reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.

    SELF-ALIGNED NANODOTS FOR 3D NAND FLASH MEMORY
    8.
    发明申请
    SELF-ALIGNED NANODOTS FOR 3D NAND FLASH MEMORY 审中-公开

    公开(公告)号：US20180233359A1

    公开(公告)日：2018-08-16

    申请号：US15881405

    申请日：2018-01-26

    Applicant: Applied Materials, Inc.

    Inventor： Sungwon JUN ,  Saurabh CHOPRA ,  Thomas Jongwan KWON ,  Er-Xuan PING

    IPC: H01L21/02 ,  C23C16/06

    Abstract: A method of forming a 3D NAND structure having self-aligned nanodots includes depositing alternating layers of an oxide and a nitride on a substrate; at least partially recessing the nitride layers; and forming SiGe nanodots on the nitride layers. A method of forming a 3D NAND structure having self-aligned nanodots includes depositing alternating layers of an oxide and a nitride on a substrate; at least partially recessing the nitride layers; and forming SiGe nanodots on the nitride layers by a process including maintaining a temperature of the substrate below about 560° C.; flowing a silicon epitaxy precursor into the chamber; forming a silicon epitaxial layer on the substrate at the nitride layers; flowing germanium gas into the chamber with the silicon epitaxy precursor; and forming a silicon germanium epitaxial layer on the substrate at the nitride layers.

    APPARATUS AND METHODS FOR HEATING TUNABILITY IN PROCESSING CHAMBERS
    9.
    发明公开
    APPARATUS AND METHODS FOR HEATING TUNABILITY IN PROCESSING CHAMBERS 审中-公开

    公开(公告)号：US20240248298A1

    公开(公告)日：2024-07-25

    申请号：US18159222

    申请日：2023-01-25

    Applicant: Applied Materials, Inc.

    Inventor： Ala MORADIAN ,  Saurabh CHOPRA ,  Lori D. WASHINGTON

    IPC: G02B26/08 ,  G02B17/00 ,  H01L21/67 ,  H05B3/00

    CPC classification number: G02B26/0816 ,  G02B17/002 ,  H01L21/67115 ,  H05B3/0047

    Abstract: Embodiments herein are generally directed to electronic device manufacturing and, more particularly, to systems and methods for lamp heating in thermal processing chambers. In an embodiment, an adjustable reflector assembly includes a plurality of elements including at least one stationary element and at least one rotating element, wherein a first surface of each of the plurality of elements is a reflective surface, and at least one actuation mechanism configured to actuate the at least one rotating element relative to the stationary element. A method of processing a substrate includes measuring a thermal intensity of a thermal profile of an area of a substrate under a lamp and the reflector assembly, determining if the thermal intensity is outside of desired parameters, and in response to the thermal intensity being outside of desired parameters, and adjusting a reflector profile of the reflector assembly.

    HEAT SOURCE ARRANGEMENTS, PROCESSING CHAMBERS, AND RELATED METHODS TO FACILITATE DEPOSITION PROCESS ADJUSTABILITY
    10.
    发明公开
    HEAT SOURCE ARRANGEMENTS, PROCESSING CHAMBERS, AND RELATED METHODS TO FACILITATE DEPOSITION PROCESS ADJUSTABILITY 审中-公开

    公开(公告)号：US20240234175A9

    公开(公告)日：2024-07-11

    申请号：US17971338

    申请日：2022-10-21

    Applicant: Applied Materials, Inc.

    Inventor： Ala MORADIAN ,  Saurabh CHOPRA

    IPC: H01L21/67

    CPC classification number: H01L21/67115 ,  H01L21/67207

    Abstract: The present disclosure relates to heat source arrangements, processing chambers, and related methods to facilitate deposition process adjustability. In one implementation, a processing chamber applicable for use in semiconductor manufacturing includes a lower window and an upper window. The lower window and the upper window at least partially define an internal volume. The processing chamber includes a substrate support disposed in the internal volume, and the substrate support includes a support face. The processing chamber includes one or more inner heat sources. Each inner heat source of the one or more inner heat sources is oriented substantially parallel to a surface of the support face. The processing chamber includes one or more outer heat sources disposed outwardly of the inner heat sources. Each outer heat source of the one or more outer heat sources is oriented nonparallel to the surface of the support face.

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