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    Methods for forming an interconnect pattern on a substrate
    1.
    发明授权
    Methods for forming an interconnect pattern on a substrate 有权
    在基板上形成布线图形的方法

    公开(公告)号：US09437479B2

    公开(公告)日：2016-09-06

    申请号：US14523302

    申请日：2014-10-24

    申请人： APPLIED MATERIALS, INC.

    发明人： Suketu A. Parikh ,  Mehul Naik

    IPC分类号： H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/76802 ,  H01L21/7682 ,  H01L21/7684 ,  H01L2221/1047

    摘要： Embodiments of methods for forming interconnect patterns on a substrate are provided herein. In some embodiments, a method for forming an interconnect pattern atop a substrate includes depositing a porous dielectric layer atop a cap layer and a plurality of spacers disposed atop the cap layer, wherein the cap layer is disposed atop a bulk dielectric layer and the bulk dielectric layer is disposed atop a substrate; removing a portion of the porous dielectric layer; removing the plurality of spacers to form features in the porous dielectric layer; and etching the cap layer to extend the features through the cap layer.

    摘要翻译： 本文提供了在衬底上形成互连图案的方法的实施例。 在一些实施例中，用于在衬底顶部形成互连图案的方法包括在顶盖顶部沉积多孔电​​介质层，以及设置在顶盖顶部的多个间隔物，其中所述覆盖层设置在体电介质层的顶部， 层设置在基板的顶部; 去除所述多孔介电层的一部分; 去除所述多个间隔物以在所述多孔介电层中形成特征; 并且蚀刻所述盖层以通过所述盖层延伸所述特征。

    SIMULTANEOUS METAL PATTERNING FOR 3D INTERCONNECTS
    2.
    发明申请
    SIMULTANEOUS METAL PATTERNING FOR 3D INTERCONNECTS 审中-公开

    公开(公告)号：US20200091002A1

    公开(公告)日：2020-03-19

    申请号：US16570436

    申请日：2019-09-13

    申请人： Applied Materials, Inc.

    发明人： Suketu A. Parikh

    IPC分类号： H01L21/822 ,  H01L21/32 ,  H01L21/762 ,  H01L21/027

    摘要： Processing methods may be performed to produce three-dimensional interconnects on a substrate. The methods may include forming a first metal interconnect layer over a semiconductor substrate. The methods may include forming a first dielectric layer over the first metal interconnect layer. The methods may include forming a second metal interconnect layer over the first dielectric layer. The methods may include forming a patterning mask overlying the second metal interconnect layer. The methods may also include simultaneously etching each of the first metal interconnect layer, the first dielectric layer, and the second metal interconnect layer to expose the substrate to produce a multilayer interconnect structure in a first lateral direction.

    Methods and apparatus for fabrication of self aligning interconnect structure
    4.
    发明授权
    Methods and apparatus for fabrication of self aligning interconnect structure 有权

    公开(公告)号：US11049770B2

    公开(公告)日：2021-06-29

    申请号：US16827814

    申请日：2020-03-24

    申请人： APPLIED MATERIALS, INC.

    发明人： Suketu A. Parikh

    IPC分类号： H01L21/768 ,  H01L21/3213

    摘要： Methods and apparatus for forming an interconnect structure, including: depositing a plurality of spacers atop a low-k dielectric layer including a plurality of recessed vias, wherein one or more of the plurality of spacers is deposited atop the top surface of the low-k dielectric layer and within one or more of the plurality of recessed vias to form a one or more partially filled recessed vias; depositing a conformal metal layer atop the low-k dielectric layer, plurality of spacers, and within the one or more partially filled recessed vias to form a plurality of filled vias; etching the conformal metal layer to remove portions thereof to form a second plurality of partially filled recessed vias; and filling between the plurality spacers and within the second plurality of partially filled recessed vias with a dielectric material to form a second plurality of filled vias.

    SYSTEMS AND METHODS FOR IMPROVED PERFORMANCE IN SEMICONDUCTOR PROCESSING
    6.
    发明申请
    SYSTEMS AND METHODS FOR IMPROVED PERFORMANCE IN SEMICONDUCTOR PROCESSING 审中-公开

    公开(公告)号：US20200091018A1

    公开(公告)日：2020-03-19

    申请号：US16131942

    申请日：2018-09-14

    申请人： Applied Materials, Inc.

    发明人： Chirantha P. Rodrigo ,  Suketu A. Parikh ,  Tsz Keung Cheung ,  Satya Gowthami Achanta ,  Jingchun Zhang ,  Saravjeet Singh ,  Tae Won Kim

    IPC分类号： H01L21/66 ,  H01L21/3065 ,  H01J37/32

    摘要： Exemplary etching methods may include flowing a hydrogen-containing precursor into a semiconductor processing chamber. The methods may include flowing a fluorine-containing precursor into a remote plasma region of the semiconductor processing chamber. The methods may include forming a plasma of the fluorine-containing precursor in the remote plasma region. The methods may include etching a pre-determined amount of a silicon-containing material from a substrate in a processing region of the semiconductor processing chamber. The methods may include measuring a radical density within the remote plasma region during the etching. The methods may also include halting the flow of the hydrogen-containing precursor into the semiconductor processing chamber when the radical density measured over time correlates to a produced amount of etchant to remove the pre-determined amount of the silicon-containing material.