公开(公告)号：US09018108B2

公开(公告)日：2015-04-28

申请号：US13834333

申请日：2013-03-15

Applicant: Applied Materials, Inc.

Inventor： Sukwon Hong ,  Toan Tran ,  Abhijit Mallick ,  Jingmei Liang ,  Nitin K. Ingle

IPC: H01L21/31 ,  H01L21/02 ,  C23C16/56 ,  C23C16/452 ,  C23C16/34

CPC classification number: H01L21/02274 ,  C23C16/045 ,  C23C16/345 ,  C23C16/401 ,  C23C16/452 ,  C23C16/45565 ,  C23C16/45574 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/0234

Abstract: Methods of forming a dielectric layer on a substrate are described, and may include introducing a first precursor into a remote plasma region fluidly coupled with a substrate processing region of a substrate processing chamber A plasma may be formed in the remote plasma region to produce plasma effluents. The plasma effluents may be directed into the substrate processing region. A silicon-containing precursor may be introduced into the substrate processing region, and the silicon-containing precursor may include at least one silicon-silicon bond. The plasma effluents and silicon-containing precursor may be reacted in the processing region to form a silicon-based dielectric layer that is initially flowable when formed on the substrate.

Abstract translation: 描述了在基板上形成电介质层的方法，并且可以包括将第一前体引入到与衬底处理室的衬底处理区域流体耦合的远程等离子体区域中。等离子体可以形成在远程等离子体区域中以产生等离子体流出物 。 等离子体流出物可以被引导到基板处理区域中。 可以将含硅前体引入衬底处理区域，并且含硅前体可以包括至少一个硅 - 硅键。 等离子体流出物和含硅前体可以在处理区域中反应以形成当在基底上形成时最初可流动的硅基电介质层。

公开(公告)号：US20130288485A1

公开(公告)日：2013-10-31

申请号：US13792767

申请日：2013-03-11

Applicant: APPLIED MATERIALS, INC.

Inventor： Jingmei Liang ,  Sukwon Hong ,  Jun Tae Choi

IPC: H01L21/02

CPC classification number: H01L21/02271 ,  C23C16/56 ,  H01J37/321 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/0234

Abstract: A method of forming a dielectric layer is described. The method first deposits an initially-flowable layer on a substrate. The initially-flowable layer is then densified by exposing the substrate to a high-density plasma (HDP). Essentially no additional material is deposited on the initially-flowable layer, in embodiments, but the impact of the accelerated ionic species serves to condense the layer and increase the etch tolerance of the processed layer.

Abstract translation: 描述形成电介质层的方法。 该方法首先在基底上沉积初始可流动的层。 然后通过将衬底暴露于高密度等离子体（HDP）来将初始可流动层致密化。 在实施方案中基本上没有另外的材料沉积在初始可流动的层上，但加速的离子物质的影响用于冷凝层并增加处理层的蚀刻耐受性。

公开(公告)号：US08975152B2

公开(公告)日：2015-03-10

申请号：US13669184

申请日：2012-11-05

Applicant: Applied Materials, Inc.

Inventor： Sukwon Hong ,  Hiroshi Hamana ,  Jingmei Liang

IPC: H01L21/76 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/306 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/306 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/76229

Abstract: Methods of reducing dislocation in a semiconductor substrate between asymmetrical trenches are described. The methods may include etching a plurality of trenches on a semiconductor substrate and may include two adjacent trenches of unequal width separated by an unetched portion of the substrate. The methods may include forming a layer of dielectric material on the substrate. The dielectric material may form a layer in the trenches located adjacent to each other of substantially equivalent height on both sides of the unetched portion of the substrate separating the two trenches. The methods may include densifying the layer of dielectric material so that the densified dielectric within the two trenches of unequal width exerts a substantially similar stress on the unetched portion of the substrate that separates them.

Abstract translation: 描述了在不对称沟槽之间减少半导体衬底中的位错的方法。 所述方法可以包括蚀刻半导体衬底上的多个沟槽，并且可以包括由衬底的未蚀刻部分分开的不相等宽度的两个相邻沟槽。 所述方法可以包括在基底上形成电介质材料层。 介电材料可以在分离两个沟槽的衬底的未蚀刻部分的两侧上在相邻的基本相当的高度的沟槽中形成层。 所述方法可以包括使介电材料层致密化，使得在不同宽度的两个沟槽内的致密电介质对基板的未蚀刻部分施加基本相似的应力。

公开(公告)号：US20130309870A1

公开(公告)日：2013-11-21

申请号：US13669184

申请日：2012-11-05

Applicant: Applied Materials, Inc.

Inventor： Sukwon Hong ,  Hiroshi Hamana ,  Jingmei Liang

IPC: H01L21/306

CPC classification number: H01L21/306 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/76229

Abstract: Methods of reducing dislocation in a semiconductor substrate between asymmetrical trenches are described. The methods may include etching a plurality of trenches on a semiconductor substrate and may include two adjacent trenches of unequal width separated by an unetched portion of the substrate. The methods may include forming a layer of dielectric material on the substrate. The dielectric material may form a layer in the trenches located adjacent to each other of substantially equivalent height on both sides of the unetched portion of the substrate separating the two trenches. The methods may include densifying the layer of dielectric material so that the densified dielectric within the two trenches of unequal width exerts a substantially similar stress on the unetched portion of the substrate that separates them.

Abstract translation: 描述了在不对称沟槽之间减少半导体衬底中位错的方法。 所述方法可以包括蚀刻半导体衬底上的多个沟槽，并且可以包括由衬底的未蚀刻部分分开的不相等宽度的两个相邻沟槽。 所述方法可以包括在基底上形成电介质材料层。 介电材料可以在分离两个沟槽的衬底的未蚀刻部分的两侧上在相邻的基本相当的高度的沟槽中形成层。 所述方法可以包括使介电材料层致密化，使得在不同宽度的两个沟槽内的致密电介质对基板的未蚀刻部分施加基本相似的应力。

公开(公告)号：US20140329027A1

公开(公告)日：2014-11-06

申请号：US13955640

申请日：2013-07-31

Applicant: Applied Materials, Inc.

Inventor： Jingmei Liang ,  Nitin K. Ingle ,  Sukwon Hong ,  Abhishek Dube ,  DongQing Li

IPC: B05D3/10 ,  B05D3/06 ,  B05D3/02

CPC classification number: C23C16/56 ,  C23C16/401 ,  C23C16/452 ,  C23C16/50

Abstract: Methods of forming gapfill silicon-containing layers are described. The methods may include providing or forming a silicon-and-hydrogen-containing layer on a patterned substrate. The methods include non-thermally treating the silicon-and-hydrogen-containing layer at low substrate temperature to increase the concentration of Si—Si bonds while the silicon-and-hydrogen-containing layer remains soft. The flaccid layer is able to adjust to the departure of hydrogen from the film and retain a high density without developing a stress. Film qualify is further improved by then inserting O between Si—Si bonds to expand the film in the trenches thereby converting the silicon-and-hydrogen-containing layer to a silicon-and-oxygen-containing layer.

Abstract translation: 描述形成间隙填充含硅层的方法。 所述方法可以包括在图案化衬底上提供或形成含硅和氢的层。 这些方法包括在低衬底温度下非热处理含硅和氢的层以增加Si-Si键的浓度，同时含硅和氢的层保持柔软。 松弛层能够适应于离开膜的氢离子并保持高密度而不产生应力。 然后通过在Si-Si键之间插入O以使沟槽中的膜膨胀，从而将含硅和含氢层转化为含硅和氧的层，进一步改善了膜合格性。

公开(公告)号：US20140213070A1

公开(公告)日：2014-07-31

申请号：US13834333

申请日：2013-03-15

Applicant: Applied Materials, Inc.

Inventor： Sukwon Hong ,  Toan Tran ,  Abhijit Mallick ,  Jingmei Liang ,  Nitin K. Ingle

IPC: H01L21/02

CPC classification number: H01L21/02274 ,  C23C16/045 ,  C23C16/345 ,  C23C16/401 ,  C23C16/452 ,  C23C16/45565 ,  C23C16/45574 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/0234

Abstract: Methods of forming a dielectric layer on a substrate are described, and may include introducing a first precursor into a remote plasma region fluidly coupled with a substrate processing region of a substrate processing chamber A plasma may be formed in the remote plasma region to produce plasma effluents. The plasma effluents may be directed into the substrate processing region. A silicon-containing precursor may be introduced into the substrate processing region, and the silicon-containing precursor may include at least one silicon-silicon bond. The plasma effluents and silicon-containing precursor may be reacted in the processing region to form a silicon-based dielectric layer that is initially flowable when formed on the substrate.

Abstract translation: 描述了在基板上形成电介质层的方法，并且可以包括将第一前体引入到与衬底处理室的衬底处理区域流体耦合的远程等离子体区域中。等离子体可以形成在远程等离子体区域中以产生等离子体流出物 。 等离子体流出物可以被引导到基板处理区域中。 可以将含硅前体引入衬底处理区域，并且含硅前体可以包括至少一个硅 - 硅键。 等离子体流出物和含硅前体可以在处理区域中反应以形成当在基底上形成时最初可流动的硅基电介质层。