SEMICONDUCTOR DEVICE WITH A DYNAMIC GATE-DRAIN CAPACITANCE
    1.
    发明申请
    SEMICONDUCTOR DEVICE WITH A DYNAMIC GATE-DRAIN CAPACITANCE 有权
    具有动态栅极导通电容的半导体器件

    公开(公告)号:US20130009227A1

    公开(公告)日:2013-01-10

    申请号:US13614479

    申请日:2012-09-13

    IPC分类号: H01L27/07 H01L21/8234

    摘要: A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.

    摘要翻译: 具有动态栅极漏极电容的半导体器件。 一个实施例提供一种半导体器件。 该器件包括半导体衬底,场效应晶体管结构,其包括源区,第一体区,漏区,栅电极结构和栅极绝缘层。 栅极绝缘层设置在栅电极结构和体区之间。 栅极电极结构和漏极区域部分地形成电容器结构,其包括栅极 - 漏极电容,该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地 栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值,或者在给定的反向电压下包括平台状过程。

    SEMICONDUCTOR DEVICE WITH A DYNAMIC GATE-DRAIN CAPACITANCE
    2.
    发明申请
    SEMICONDUCTOR DEVICE WITH A DYNAMIC GATE-DRAIN CAPACITANCE 有权
    具有动态栅极导通电容的半导体器件

    公开(公告)号:US20100025748A1

    公开(公告)日:2010-02-04

    申请号:US12184819

    申请日:2008-08-01

    IPC分类号: H01L29/94 H01L21/8234

    摘要: A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.

    摘要翻译: 具有动态栅极漏极电容的半导体器件。 一个实施例提供一种半导体器件。 该器件包括半导体衬底,场效应晶体管结构,其包括源区,第一体区,漏区,栅电极结构和栅极绝缘层。 栅极绝缘层设置在栅电极结构和体区之间。 栅极电极结构和漏极区域部分地形成电容器结构,其包括栅极 - 漏极电容,该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地 栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值,或者在给定的反向电压下包括平台状过程。

    SEMICONDUCTOR COMPONENT WITH TWO-STAGE BODY ZONE
    3.
    发明申请
    SEMICONDUCTOR COMPONENT WITH TWO-STAGE BODY ZONE 审中-公开
    具有两级机体区域的半导体组件

    公开(公告)号:US20090321818A1

    公开(公告)日:2009-12-31

    申请号:US12164611

    申请日:2008-06-30

    IPC分类号: H01L29/78 H01L21/336

    摘要: A semiconductor component with a two-stage body zone. One embodiment provides semiconductor component including a drift zone, and a compensation zone of a second conduction type. The compensation zone is arranged in the drift zone. A source zone and a body zone is provided. The body zone is arranged between the source zone and the drift zone. A gate electrode is arranged adjacent to the body zone. The body zone has a first body zone section and a second body zone section, which are adjacent to one another along the gate dielectric and of which the first body zone section is doped more highly than the second body zone section.

    摘要翻译: 具有两级体区的半导体元件。 一个实施例提供了包括漂移区和第二导电类型的补偿区的半导体元件。 补偿区设置在漂移区。 提供源区和体区。 身体区域布置在源区和漂移区之间。 栅电极邻近身体区域布置。 身体区域具有沿着栅极电介质彼此相邻的第一身体区段和第二身体区段部分,并且第一身体区域部分被掺杂得比第二身体区段更高。

    Semiconductor device with a dynamic gate-drain capacitance
    5.
    发明授权
    Semiconductor device with a dynamic gate-drain capacitance 有权
    具有动态栅极 - 漏极电容的半导体器件

    公开(公告)号:US08829584B2

    公开(公告)日:2014-09-09

    申请号:US13614479

    申请日:2012-09-13

    IPC分类号: H01L27/07

    摘要: A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.

    摘要翻译: 具有动态栅极漏极电容的半导体器件。 一个实施例提供一种半导体器件。 该器件包括半导体衬底,场效应晶体管结构,其包括源区,第一体区,漏区,栅电极结构和栅极绝缘层。 栅极绝缘层设置在栅电极结构和体区之间。 栅极电极结构和漏极区域部分地形成电容器结构,其包括栅极 - 漏极电容,该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地 栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值,或者在给定的反向电压下包括平台状过程。

    Semiconductor with a dynamic gate-drain capacitance
    6.
    发明授权
    Semiconductor with a dynamic gate-drain capacitance 有权
    具有动态栅极 - 漏极电容的半导体

    公开(公告)号:US08273622B2

    公开(公告)日:2012-09-25

    申请号:US13161050

    申请日:2011-06-15

    IPC分类号: H01L29/94

    摘要: A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.

    摘要翻译: 具有动态栅极漏极电容的半导体器件。 一个实施例提供一种半导体器件。 该器件包括半导体衬底,场效应晶体管结构,其包括源区,第一体区,漏区,栅电极结构和栅极绝缘层。 栅极绝缘层设置在栅电极结构和体区之间。 栅极电极结构和漏极区域部分地形成电容器结构,其包括栅极 - 漏极电容,该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地 栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值,或者在给定的反向电压下包括平台状过程。

    SEMICONDUCTOR WITH A DYNAMIC GATE-DRAIN CAPACITANCE
    7.
    发明申请
    SEMICONDUCTOR WITH A DYNAMIC GATE-DRAIN CAPACITANCE 有权
    具有动态栅极电容的半导体

    公开(公告)号:US20110244646A1

    公开(公告)日:2011-10-06

    申请号:US13161050

    申请日:2011-06-15

    IPC分类号: H01L21/336

    摘要: A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.

    摘要翻译: 具有动态栅极漏极电容的半导体器件。 一个实施例提供一种半导体器件。 该器件包括半导体衬底,场效应晶体管结构,其包括源区,第一体区,漏区,栅电极结构和栅极绝缘层。 栅极绝缘层设置在栅电极结构和体区之间。 栅极电极结构和漏极区域部分地形成电容器结构,其包括栅极 - 漏极电容,该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地 栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值,或者在给定的反向电压下包括平台状过程。

    Semiconductor device with a dynamic gate-drain capacitance
    8.
    发明授权
    Semiconductor device with a dynamic gate-drain capacitance 有权
    具有动态栅极 - 漏极电容的半导体器件

    公开(公告)号:US07982253B2

    公开(公告)日:2011-07-19

    申请号:US12184819

    申请日:2008-08-01

    IPC分类号: H01L29/94

    摘要: A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.

    摘要翻译: 具有动态栅极漏极电容的半导体器件。 一个实施例提供一种半导体器件。 该器件包括半导体衬底,场效应晶体管结构,其包括源区,第一体区,漏区,栅电极结构和栅极绝缘层。 栅极绝缘层设置在栅电极结构和体区之间。 栅极电极结构和漏极区域部分地形成电容器结构,其包括栅极 - 漏极电容,该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地改变。 栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值,或者在给定的反向电压下包括平台状过程。

    SEMICONDUCTOR DEVICE WITH INHERENT CAPACITANCES AND METHOD FOR ITS PRODUCTION
    9.
    发明申请
    SEMICONDUCTOR DEVICE WITH INHERENT CAPACITANCES AND METHOD FOR ITS PRODUCTION 有权
    具有固有电容的半导体器件及其制造方法

    公开(公告)号:US20090224302A1

    公开(公告)日:2009-09-10

    申请号:US12043429

    申请日:2008-03-06

    IPC分类号: H01L29/94 H01L21/8238

    摘要: A semiconductor device with inherent capacitances and method for its production. The semiconductor device has an inherent feedback capacitance between a control electrode and a first electrode. In addition, the semiconductor device has an inherent drain-source capacitance between the first electrode and a second electrode. At least one monolithically integrated additional capacitance is connected in parallel to the inherent feedback capacitance or in parallel to the inherent drain-source capacitance. The additional capacitance comprises a first capacitor surface and a second capacitor surface opposite the first capacitor surface. The capacitor surfaces are structured conductive layers of the semiconductor device on a front side of the semiconductor body, between which a dielectric layer is located and which form at least one additional capacitor.

    摘要翻译: 具有固有电容的半导体器件及其制造方法。 半导体器件在控制电极和第一电极之间具有固有的反馈电容。 此外,半导体器件在第一电极和第二电极之间具有固有的漏极 - 源极电容。 至少一个单片集成附加电容与固有反馈电容并联连接,或与固有漏 - 源电容并联连接。 附加电容包括与第一电容器表面相对的第一电容器表面和第二电容器表面。 电容器表面是半导体器件的前侧上的半导体器件的结构化导电层,介电层位于其之间,并形成至少一个附加电容器。