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    Indicating acknowledge of stable state of pipeline resource when freeze bit set and context switch inhibited
    3.
    发明授权
    Indicating acknowledge of stable state of pipeline resource when freeze bit set and context switch inhibited 有权
    指示当冻结位设置和上下文切换禁止时管道资源稳定状态的确认

    公开(公告)号：US07467289B1

    公开(公告)日：2008-12-16

    申请号：US11553913

    申请日：2006-10-27

    申请人： Lincoln G. Garlick ,  Vikramjeet Singh ,  David W. Nuechterlein ,  Shail Dave ,  Jeffrey M. Smith ,  Paolo E. Sabella ,  Dennis K. Ma

    发明人： Lincoln G. Garlick ,  Vikramjeet Singh ,  David W. Nuechterlein ,  Shail Dave ,  Jeffrey M. Smith ,  Paolo E. Sabella ,  Dennis K. Ma

    IPC分类号： G06F11/30

    CPC分类号： G06F9/485

    摘要： Software can freeze portions of a pipeline operation in a processor by asserting a predetermined freeze register in the processor. The processor halts operations relating to portions of a common pipeline processing in response to an asserted freeze register. Processor resources that operate downstream from the common pipeline continue to process any scheduled instructions. The processor is prevented from initiating any context switching in which a processor resource is allocated to a different channel. The processor stops supplying any additional data to downstream resources and ensures that the interface to downstream resources is clear of previously sent data. The processor prevents state machines from making additional requests. The processor asserts an acknowledgement indication in response to the freeze assertion when the processing has reached a stable state. Software is allowed to manipulate states and registers within the processor. Clearing the freeze register allows processing to resume.

    摘要翻译： 软件可以通过在处理器中断言预定的冻结寄存器来冻结处理器中流水线操作的部分。 响应于断言的冻结寄存器，处理器停止与公共流水线处理的部分有关的操作。 在公共管道下游运行的处理器资源继续处理任何计划的指令。 防止处理器发起其中将处理器资源分配给不同信道的任何上下文切换。 处理器停止向下游资源提供任何附加数据，并确保与下游资源的接口清除以前发送的数据。 处理器可防止状态机发出其他请求。 当处理已经达到稳定状态时，处理器响应于冻结断言声明确认指示。 允许软件在处理器内操纵状态和寄存器。 清除冻结寄存器允许处理恢复。

    Asynchronous interface for communicating between clock domains
    4.
    发明授权
    Asynchronous interface for communicating between clock domains 有权
    用于在时钟域之间通信的异步接口

    公开(公告)号：US08547993B1

    公开(公告)日：2013-10-01

    申请号：US11463682

    申请日：2006-08-10

    申请人： Lincoln G. Garlick ,  Richard A. Silkebakken ,  Prakash G. Apte ,  Paolo E. Sabella ,  Samuel H. Duncan ,  Dennis K. Ma ,  Sean J. Treichler

    发明人： Lincoln G. Garlick ,  Richard A. Silkebakken ,  Prakash G. Apte ,  Paolo E. Sabella ,  Samuel H. Duncan ,  Dennis K. Ma ,  Sean J. Treichler

    IPC分类号： H04L12/66 ,  H04L29/06

    CPC分类号： H04L29/06 ,  G06F13/4226

    摘要： Methods, apparatuses, and systems are presented for performing asynchronous communications involving using an asynchronous interface to send signals between a source device and a plurality of client devices, the source device and the plurality of client devices being part of a processing unit capable of performing graphics operations, the source device being coupled to the plurality of client devices using the asynchronous interface, wherein the asynchronous interface includes at least one request signal, at least one address signal, at least one acknowledge signal, and at least one data signal, and wherein the asynchronous interface operates in accordance with at least one programmable timing characteristic associated with the source device.

    摘要翻译： 呈现用于执行涉及使用异步接口在源设备和多个客户端设备之间发送信号的异步通信的方法，设备和系统，源设备和多个客户端设备是能够执行图形的处理单元的一部分 所述源设备使用所述异步接口耦合到所述多个客户端设备，其中所述异步接口包括至少一个请求信号，至少一个地址信号，至少一个确认信号和至少一个数据信号，并且其中 异步接口根据与源设备相关联的至少一个可编程定时特性进行操作。

    Method and apparatus for context switching of multiple engines
    6.
    发明授权
    Method and apparatus for context switching of multiple engines 有权
    多台发动机上下文切换的方法和装置

    公开(公告)号：US08108879B1

    公开(公告)日：2012-01-31

    申请号：US11553901

    申请日：2006-10-27

    申请人： Lincoln G. Garlick ,  Dennis K. Ma ,  Paolo E. Sabella ,  David W. Nuechterlein

    发明人： Lincoln G. Garlick ,  Dennis K. Ma ,  Paolo E. Sabella ,  David W. Nuechterlein

    IPC分类号： G06F9/46

    CPC分类号： G06F9/52

    摘要： A processor having multiple independent engines can concurrently support a number of independent processes or operation contexts. The processor can independently schedule instructions for execution by the engines. The processor can independently switch the operation context that an engine supports. The processor can maintain the integrity of the operations performed and data processed by each engine during a context switch by controlling the manner in which the engine transitions from one operation context to the next. The processor can wait for the engine to complete processing of pipelined instructions of a first context before switching to another context, or the processor can halt the operation of the engine in the midst of one or more instructions to allow the engine to execute instructions corresponding to another context. The processor can affirmatively verify completion of tasks for a specific operation context.

    摘要翻译： 具有多个独立引擎的处理器可以同时支持多个独立的进程或操作上下文。 处理器可以独立地调度指令以供引擎执行。 处理器可以独立地切换引擎支持的操作上下文。 处理器可以通过控制引擎从一个操作上下文转换到下一个操作上下文的方式来保持在上下文切换期间由每个引擎执行的操作和数据处理的完整性。 处理器可以等待引擎在切换到另一个上下文之前完成对第一上下文的流水线指令的处理，或者处理器可以在一个或多个指令中停止发动机的操作，以允许引擎执行对应于 另一个上下文。 处理器可以肯定地验证特定操作上下文的任务完成。

    Zero frame buffer
    7.
    发明授权
    Zero frame buffer 有权
    零帧缓冲区

    公开(公告)号：US07483032B1

    公开(公告)日：2009-01-27

    申请号：US11253438

    申请日：2005-10-18

    申请人： Sonny S. Yeoh ,  Shane J. Keil ,  Dennis K. Ma ,  Peter C. Tong

    发明人： Sonny S. Yeoh ,  Shane J. Keil ,  Dennis K. Ma ,  Peter C. Tong

    IPC分类号： G06F12/00 ,  G06F15/16 ,  G06F12/08

    CPC分类号： G09G5/363

    摘要： Circuits, methods, and apparatus that allow the elimination of a frame buffer connected directly to a graphics processing unit. The graphics processing unit includes an on-chip memory. Following system power-up or reset, the GPU initially renders comparatively low-resolution images to the on-chip memory for display. Afterward, the GPU renders images, which are typically higher resolution, and stores them in a system memory, apart from the graphics processing unit. The on-chip memory, which is no longer needed for image storage, instead stores address information, referred to as page tables, identifying the location of data stored by the GPU in the separate system memory.

    摘要翻译： 允许消除直接连接到图形处理单元的帧缓冲器的电路，方法和装置。 图形处理单元包括片上存储器。 在系统上电或复位后，GPU最初将相对较低分辨率的图像呈现给片上存储器进行显示。 之后，GPU将呈现通常较高分辨率的图像，并将它们存储在除了图形处理单元之外的系统存储器中。 不再需要用于图像存储的片上存储器，而是存储称为页表的地址信息，其将GPU存储的数据的位置识别在单独的系统存储器中。

    Providing byte enables for peer-to-peer data transfer within a computing environment
    10.
    发明授权
    Providing byte enables for peer-to-peer data transfer within a computing environment 有权
    提供字节可以在计算环境中进行对等数据传输

    公开(公告)号：US09424227B2

    公开(公告)日：2016-08-23

    申请号：US13541633

    申请日：2012-07-03

    申请人： Samuel H. Duncan ,  Dennis K. Ma ,  Wei-Je Huang ,  Gary Ward

    发明人： Samuel H. Duncan ,  Dennis K. Ma ,  Wei-Je Huang ,  Gary Ward

    IPC分类号： G06F15/173 ,  G06F15/167 ,  G06F15/16 ,  G06F15/163 ,  G06F15/17

    CPC分类号： G06F15/167 ,  G06F15/16 ,  G06F15/163 ,  G06F15/17 ,  G06F15/173

    摘要： Non-contiguous or tiled payload data are efficiently transferred between peers over a fabric. Specifically, a client transfers a byte enable message to a peer device via a mailbox mechanism, where the byte enable message specifies which bytes of the payload data being transferred via the data packet are to be written to the frame buffer on the peer device and which bytes are not to be written. The client transfers the non-contiguous or tiled payload payload data to the peer device. Upon receiving the payload data, the peer device writes bytes from the payload data into the target frame buffer for only those bytes enabled via the byte enable message. One advantage of the present invention is that non-contiguous or tiled data are transferred over a fabric with improved efficiency.

    摘要翻译： 非连续或平铺的有效载荷数据可以通过一个结构在对等体之间有效传输。 具体来说，客户端通过邮箱机制向对等设备传送字节使能消息，其中字节使能消息指定要经由数据包传送的有效载荷数据的哪些字节将被写入对等设备上的帧缓冲器，以及哪个 字节不被写入。 客户端将非连续或平铺的有效载荷有效载荷数据传输到对等设备。 在接收到有效载荷数据时，对等设备将字节从有效载荷数据写入目标帧缓冲器，以便仅通过字节使能消息使能的字节。 本发明的一个优点在于，不连续的或平铺的数据以提高的效率在织物上传送。